Ejaz Haq

A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth

This paper describes a 32-bank 1 Gb DRAM achieving 1 Gbyte/s (500 Mb/s/DQ pin) data bandwidth and the access time from RAS of 31 ns at V/sub cc/=2.0 V and 25/spl deg/C. The chip employs (1) a merged multibank architecture to minimize die area; (2) an extended small swing read operation and a single I/O line driving write scheme to reduce power consumption; (3) a self-strobing I/O schemes to achieve high bandwidth with low power dissipation; and (4) a block redundancy scheme with increased flexibility. The nonstitched chip with an area of 652 mm/sup 2/ has been fabricated using 0.16 /spl mu/m four-poly, four-metal CMOS process technology.

Variable V/sub CC/ design techniques for battery-operated DRAMs

Wide-voltage-range DRAMs with extended data retention are desirable for battery-operated or portable computers and consumer devices. The techniques required to obtain wide operation, functionality, and performance of standard DRAMs from 1.8 V (two NiCd or alkaline batteries) to 3.6 V (upper end of LVTTL standard) are described. Specific techniques shown are: (1) a low-power and low-voltage reference generator for detecting V/sub CC/ level; (2) compensation of DC generators, V/sub BB/ and V/sub PP/, for obtaining high speed at reduced voltages; (3) a static word-line driver and latch-isolation sense amplifier for reducing operating current; and (4) a programmable V/sub CC/ variable self-refresh scheme for obtaining maximum data retention time over a full operating range. A sub-50-ns access time is obtained for a 16 M DRAM (2 M*8) by simulation. >

A 3.3-V single power supply 16-Mb nonvolatile virtual DRAM using a NAND flash memory technology

A 3.3-V 16-Mb nonvolatile memory having operation virtually identical to DRAM with package pin compatibility has been developed. Read and write operations are fully DRAM compatible except for a longer RAS precharge time after write. Fast random access time of 63 ns with the NAND flash memory cell is achieved by using a hierarchical row decoder scheme and a unique folded bit-line architecture which also allows bit-by-bit program verify and inhibit operation. Fast page mode with a column address access time of 21 ns is achieved by sensing and latching 4 k cells simultaneously. To allow byte alterability, nonvolatile restore operation with self-contained erase is developed. Self-contained erase is word-line based, and increased cell disturb due to the word-line based erase is relaxed by adding a boosted bit-line scheme to a conventional self-boosting technique. The device is fabricated in a 0.5-/spl mu/m triple-well, p-substrate CMOS process using two-metal and three-poly interconnect layers. A resulting die size is 86.6 mm/sup 2/, and the effective cell size including the overhead of string select transistors is 2.0 /spl mu/m/sup 2/.

A 32-bank 1 Gb DRAM with 1 GB/s bandwidth

This 32-bank 1 Gb DRAM features: (1) a merged bank architecture (MBA) that results in only 3% die area penalty for 32-bank operation; (2) a source-synchronous I/O interface (SSI) that achieves 1 GB/s bandwidth with low power consumption; (3) flexible block redundancy that allows freedom of repair to anywhere within each half-Gb array; and (4) extended small swing read and single-I/O line driving write which result in 30% power reduction. The DRAM chip is implemented in a 0.16 /spl mu/m twin-well CMOS process.

16-Mb synchronous DRAM with 125-Mbyte/s data rate

In order to keep up with the growing need for memory bandwidth at low cost, a new synchronous DRAM (SDRAM) architecture is proposed. The SDRAM has programmable latency, burst length, and burst type for wide variety of applications. The experimental 16M SDRAM (2M/spl times/8) achieves a 125-Mbyte/s data rate using 0.5-/spl mu/m twin well CMOS technology. >

Battery Operated 16m Dram With Post Package Programmable And Variable Self Refresh

with wide operating voltage range of 1.8~ to 3.6~ for battery based portable applications. Low power during data retention is obtained with Vcc and temperature variable self refresh which is programmable after packaging using electrical fuses. High performance is achieved at low voltage with dual VPPs for well bias and on-chip high voltage power supply, dual threshold voltages for NMOS and voltage variable sensing control. The 16M has a measured RAS access time of 58ns at 1.8~ and 83°C. This paper describes a I6M DRAM

16 Mbit synchronous DRAM with 125 Mbyte/sec data rate

The rapid increase in processor performance and memory density has created the need for high bandwidth DRAM for a variety of applications. A 3.3V 2M x8 synchronous DRAM is designed with a typical data rate of 125 Mbyte/sec using internal column address sequencing, pipelined 2 bit prefetch and variable output latching scheme. It supports operating frequencies up to 125 MHz.

Look-ahead input buffer and dynamic load sensing scheme for 3.3 V ultrafast BiCMOS SRAMs

Achieving fast access time at low voltage and low power is still a demanding task for high density SRAM. Although some previous BiCMOS designs operate at 3.3 V, the access time is usually slower than at 5 V. The speed is mainly dependent on the I/O interface conversion and delay due to long data lines. We developed a look-ahead input buffer to reduce the speed delay at the input stage and a dynamic load sensing scheme to minimize the sensing delay due to long data line. A 3.3 V 1 Mbit(l28K x 8) SRAM is designed to achieve 4.5 ns access time under typical conditions using 0.5 /spl mu/m BiCMOS technology.

Variable V/sub cc/ design techniques for battery operated DRAMs

The authors describe a variable V/sub cc/ design technique to extend battery life. Several special circuits for low V/sub cc/, compensated DC generators and wordline drivers are proposed. These are implemented in a 16 M DRAM using 1 polycide, 3 poly, double-metal, and stacked capacitor based 0.4 mu m CMOS technology. The simulated speed of V/sub cc/ variable design is compared with conventional design at 25 degrees C. The slowdown below 2 V is due to threshold voltage and transistor characteristics.<<ETX>>

A 3.3 V 16 Mb nonvolatile virtual DRAM using a NAND flash memory technology

A 3.3V 16Mb nonvolatile memory has read and write operations fully DRAM-compatible except a longer RAS precharge time after write. Most systems with high-performance processors use a shadow nonvolatile memory uploaded to a fast DRAM to obtain zero wait-state performance. The introduced nonvolatile virtual DRAM (NVDRAM) eliminates the need for this redundancy, achieving high performance while reducing power consumption. Fast random access time (tRAC) with a NAND flash memory cell is achieved by using a folded bit-line architecture, and DRAM comparable column address access time (tkA) is achieved by sensing and latching 4k cells simultaneously.