Wu Gao

Design and Characteristics of a Multichannel Front-End ASIC Using Current-Mode CSA for Small-Animal PET Imaging

This paper presents the design and characteristics of a front-end readout application-specific integrated circuit (ASIC) dedicated to a multichannel-plate photodetector coupled to LYSO scintillating crystals. In our configuration, the crystals are oriented in the axial direction readout on both sides by individual photodetector channels allowing the spatial resolution and the detection efficiency to be independent of each other. Both energy signals and timing triggers from the photodetectors are required to be read out by the front-end ASIC. A current-mode charge-sensitive amplifier is proposed for this application. This paper presents performance characteristics of a 10-channel prototype chip designed and fabricated in a 0.35-μm complementary metal-oxide semiconductor process. The main results of simulations and measurements are presented and discussed. The gain of the chip is 13.1 mV/pC while the peak time of a CR-RC pulse shaper is 280 ns. The signal-to-noise ratio is 39 dB and the rms noise is 300 μV/√(Hz). The nonlinearity is less than 3% and the crosstalk is about 0.2%. The power dissipation is less than 15 mW/channel. This prototype will be extended to a 64-channel circuit with integrated time-to-digital converter and analog-to-digital converter together for a high-sensitive small-animal positron emission tomography imaging system.

Precise Multiphase Clock Generation Using Low-Jitter Delay-Locked Loop Techniques for Positron Emission Tomography Imaging

This paper presents design techniques of a multiphase clock generator using a low-jitter delay-locked loop (DLL) or its array for the developments of high-resolution multi-channel time-to-digital converters (TDCs). The low-jitter technologies for both a single DLL and an array of DLL are discussed. Based on the previous work on the design of a single DLL with 32 delay cells, an array of mixed-mode low-jitter DLLs is proposed for achieving smaller time taps. The array of DLL is successfully designed and embedded into a prototype chip of a three-channel high-resolution TDC in 0.35 CMOS process. The operational range of the DLL in the array is from 50 MHz to 120 MHz. The RMS value of measured cycle-to-cycle jitter in the DLL is about 7 ps while the peak-to-peak value is about 20 ps. A bin size of 71 ps can be achieved by using a reference clock of 100 MHz. The DNL and INL of the evaluated chip are 0.58 LSB and 0.63 LSB, respectively. The static power dissipation of the DLL array is about 23 mW.

Design and Characteristics of an Integrated Multichannel Ramp ADC Using Digital DLL Techniques for Small Animal PET Imaging

This paper presents a novel design of an integrated 12-bit multi-channel single-slope ramp analog-to-digital converter (ADC) for a small animal positron emission tomography(PET) imaging system. The proposed ADC is a part of a monolithic front-end readout application-specific integrated circuit(ASIC) which is dedicated to the detector modules consisting of LYSO scintillation crystals read out on both sides by the multi-channel plate (MCP) photodetectors. The function of the ADC is to digitize the voltage signals from a large number of readout channels. Digital delay-locked loop (DLL) techniques are proposed to realize time interpolations in order to reduce the conversion time and to enhance the resolution. Both high precision and low power are obtained. An eight-channel prototype chip is implemented in AMS 0.35 μm CMOS technology. The available resolution of the ADC is 9 ~ 12 bits. The maximum DNL and INL of the fine conversion in the ADC is ±0.75 LSB and ±0.5 LSB, respectively. The static power consumption of the ADC is 3 mW + 0.2 mW/Channel. This ADC architecture provides a possibility to integrate low-noise front-end readout circuits, time-to-digital converters and ADC together into a monolithic ASIC and to output both the energy quantity and the time information with digital representations for PET imaging systems.

Design of a 12-Bit 2.5 MS/s Integrated Multi-Channel Single-Ramp Analog-to-Digital Converter for Imaging Detector Systems

This paper presents a novel design of a 12-bit multi-channel single-ramp analog-to-digital converter (ADC) for imaging detector systems. To overcome the problem of long conversion time in the classic Wilkinson ADC, a new architecture using a counter and delay line interpolations is proposed. Two 5-bit Gray counters are designed for the coarse conversion. The time interpolation using an array of five delay-locked loops (DLLs) and the multiphase sampling technique are proposed for the fine conversion. The 140-phase delay clocks are generated by the array and pseudo 7-bit fine resolution is achieved. A one-channel prototype chip is implemented in AMS 0.35 μm CMOS technology. The total conversion time is about 400 ns, which corresponds to a sampling rate of 2.5 MS/s. The proposed ADC can be utilized in many fields, such as high-energy physics, biomedical imaging, and space applications.

Development of a Low-Noise Front-End Readout Chip Integrated With a High-Resolution TDC for APD-Based Small-Animal PET

This paper presents the design of a low-noise multi-channel front-end readout chip integrated with a high-resolution TDC. It is foreseen to be used as front-end readout electronics of Avalanche Photo Diodes (APD) dedicated to a small animal Positron Emission Tomography (PET) system. The architecture of the chip is reported. Two prototype chips, a ten-channel front-end chip and a three-channel high-resolution TDC, have been designed in AMS 0.35 μm CMOS technology. A low-noise charge-sensitive amplifier (CSA) and a shaper are integrated in each channel of the front-end chip. The proposed CSA performs a compensation of the 40 nA dark current coming from the detector. An equivalent input noise charge of 275 e- + 10 e-/pF (rms) has been obtained from test. The TDC chip is based on coarse-fine two-level conversion scheme. In the coarse conversion, a 10-bit counter is employed to achieve a wide range. Meanwhile, the time interpolation using an array of delay-locked loops is proposed for fine conversion. The measured time range is 10 μs. The bin size has been achieved from 71 ps to 142 ps with a reference clock from 100 MHz to 50 MHz.

Design of a monolithic multichannel front-end readout ASIC for PET imaging based on scintillation crystals read out by photodetectors at both ends

This paper presents the design techniques of a monolithic multichannel front-end readout chip integrated with both high-accuracy TDC and high-resolution ADC for the PET using LYSO(Ce) crystals read out by MCP PMT at both ends. In the front-end readout chain, a regulated cascade (RGC) preamplifier is employed in every channel for amplifying the current signals generated from MCP detector. A gain-adjustment stage, an integrator and a pulse shaper are employed for pulse height analysis which changes the width of the pulses. A discriminator is placed after the preamplifier to generate triggers. These triggers are sent to a sub-nanosecond TDC for measurement and digitizing. The peak values of the shaped pulses are digitized by a multichannel time-based ADC for measurement. Three prototype chips are designed in AMS 0.35 μm CMOS technology. In the front-end readout prototype chip, the dynamic range, the linearity, and the power dissipation are optimized. The input dynamic range from few fC to more than 100 pC can be achieved. The analog output range of the front-end readout circuits is from 1.2 V to 3.2 V. The shaping time is 280 ns and the power dissipation is reduced to less than 15 mW. In the TDC chip based on a DLL array, the RMS jitter and the peak-to-peak jitter of the used DLL are reduced to 7 ps and 21 ps, respectively. The bin size of the TDC has been reduced to 71ps with a reference clock of 100 MHz. In the multichannel time-based ADC chip, a maximum resolution of 12 bits, a sampling rate of ∼1 MS/s, and the power dissipation of 3 mW ° 0.2 mW/channel are achieved.

A 12-bit 2.5MS/s multi-channel ramp Analog-to-Digital Converter for Imaging detectors

This paper presents a 12-bit multi-channel ramp Analog-to-Digital Converter (ADC) for Imaging detectors dedicated to high-energy physics and biomedical imaging applications. A two-level conversion scheme is employed to reduce the conversion time. The conventional Wilkinson-type architecture with a 5-bit Gray counter is used for coarse conversion while a multiphase sampling technique is proposed for fine conversion. An array of delay-locked loop is designed to generate 140-phase clocks so as to achieve a fine resolution of 7-bit. A one-channel prototype chip is designed in 0.35 µm CMOS technology. The maximum conversion time is measured as about 400 ns, which corresponds to a sample rate of about 2.5 MS/s. The power dissipation is about 3mW/channel.

Integrated High-Resolution Multi-Channel Time-to-Digital Converters (TDCs) for PET Imaging

PET with time-of-flight (TOF) capability has been shown to provide a better reconstructed image compared to conventional positron tomography. The increase in SNR mainly depends on the size of the patient being imaged Conti (2009), the intrinsic resolution of the detector and the resolution of the TOF. In TOF-PET approach, for each detected event, the measurement of the time of flight difference between the two 511 keV photons provides an approximate value for the position of the annihilation. The approximation is directly limited to the capability of measuring the arrival time of the two photons. In the 1980s, TOF-PET were built with an achieved timing resolution of 500 ps Moses (2007). At that time, the electronics available drastically reduced the performances of the TOF-PET. Nowadays, electronics operating in the GHz range is routine and the application-specific integrated circuits (ASIC) are commonly used Ollivier-Henry et al. (2007). The ASIC needs to include a high-precision time-to-digital converter (TDC) for each detector element to reach the required time resolution(i.e., less than 100 ps)with good stability. The objective of this chapter is to review the state-of-the-art of the TDC techniques and to select proper architecture for PET imaging systems. Both the conventional TDCs and the novel TDCs are presented. The comparison of the TDC architecture is given as well.

Advances in front-end readout ASIC design for PET imaging

This paper presents the advances in design techniques of front-end ASICs for PET imaging applications. The Overview of PET front-end electronics and their features are firstly given. Secondly, the survey of the front-end ASICs dedicated to different kinds of photodetectors, signal acquisitions and imaging strategies is presented. Thirdly, the trends in the design of front-end ASICs are described. The front-end readout and analog signal processing will be replaced by digital methods via a imaging specific DSP. For the future developments, the design of front-end ASIC will focus on the one-chip solution of front-end readout circuits, high-speed digitizers and DSPs. Both hardware techniques and software skills should be employed for the front-end microelectronics system design.

A 12-bit low-power multi-channel ramp ADC using digital DLL techniques for high-energy physics and biomedical imaging

This paper presents the design of a low-power multi-channel time-based analog-to-digital converter (ADC) for the instruments dedicated to high-energy physic experiments and biomedical imaging applications. The proposed ADC is realized by using two-step conversion scheme: the voltage-to-time conversion (VTC) and the digital-to-time conversion (TDC). In VTC, the classic Wilkinson-type architecture are adopted. Both the high-precise ramp generator and the high-resolution high-speed comparator are presented. In TDC, counter-based circuits and the time interpolation based on a digital delay-locked loop (DLL) are proposed. A eight-channel prototype has been designed in AMS 0.35 #m technology. The typical resolution of the ADC is 12 bits. The typical sampling rate is about 1 Msample/s while the clock is 100 MHz. The power dissipation is 3 mW + 0.8 mW/channel. This is the first report on the design of a time-based ADC using digital DLL with low power, multiple channels and high resolution for the application of particle detections.