Xiaonan Shan

Program/erase injection current characteristics of a low-voltage low-power NROM using high-K materials as the tunnel dielectric

The program and erase injection current characteristics of a NROM with SiO2, HfO2, LaAlO3 and Al2O3 as the tunnel dielectric, respectively, are studied in this paper. Due to the lower electron and hole energy barriers introduced by LaAlO3, both the program and erase injection current densities of the NROM using LaAlO3 as the tunnel dielectric are increased dramatically. The injection efficiency is also improved significantly, which indicates that the introduction of LaAlO3 can lower the operation voltage of NROM cells. We show that the bit line voltage can be reduced to 3 V for both program and erase operations of NROM cells with LaAlO3 of 5 nm and 8 nm equivalent oxide thickness (EOT). This can greatly reduce the additional circuits to generate high voltages in a nonvolatile memory chip, meanwhile maintaining sufficient program/erase (P/E) performance and reliability. Our study also shows that the drain disturb is alleviated during programming and erasing the NROM cell with the LaAlO3 tunnel dielectric due to the lower operating voltages (VBL = 3 V). Hence a low-voltage low-power NROM flash memory device operation can be achieved by using LaAlO3 as the tunnel dielectric, due to the enhancement of the P/E injection current.

A Novel Dual-Doping Floating-Gate (DDFG) Flash Memory Featuring Low Power and High Reliability Application

In this letter, a novel Flash memory cell structure using dual doping polysilicon (p-n-p) as the floating gate, which can improve the cell performance and reliability, is proposed. Except for an additional large-angle tilted implantation, the fabrication technology is essentially compatible with standard CMOS technology. Measured results show that the new Flash cell with p-n-p-type floating gate can achieve higher programming speed, lower power, comparable erasing performance, and better data retention characteristics in comparison with conventional n-type floating-gate structure.

VDNROM: A Novel Four-Bits-Per-Cell Vertical Channel Dual-Nitride-Trapping-Layer ROM for High Density Flash Memory Applications

A novel vertical channel nonvolatile memory cell with oxide-nitride-oxide-nitride-oxide (ONONO, dual nitride trapping layers) dielectrics stack is proposed and experimentally demonstrated for the first time. Compared with the conventional planar NROM cell, since the cell area of the proposed vertical structure is independent of the gate length, the VDNROM structure can relax the limitation of the gate length scaling, and can have high capability of cell area shrinking. The fabrication process of this VDNROM device is basically compatible with planar CMOS technology. The VDNROM cell can be programmed and erased by the hot carrier injection to the localized trapping dual-nitride-layers, so it can achieve a four physical bits storage capability each cell. The reliability behaviors including the cycling endurance and the bake retention at 150degC have also been investigated and show the acceptable characteristics. The experiment results verify the VDNROM cell as a good candidate for high-density applications

Novel silicon-based flash cell structures for low power and high density memory applications

Scaling down of conventional flash memory technology faces difficult technical challenges and some physical limitations. Novel silicon-based flash cell structures were presented in this paper as possible solutions. A novel cell structure using dual doping polysilicon (PNP) as the floating gate is proposed and experimentally exhibit higher programming speed and better data retention characteristics in comparison with conventional n-type floating-gate structure. To further enhance storage density and relax the stringent requirements of scaling, a novel vertical channel dual-nitride-trapping-layer ROM (VDNROM) as a kind of SONOS flash is proposed and experimentally demonstrated. Compared with conventional planar NROM cell, VDNROM structure can have high capability of cell area shrinking and achieve four-physical-bit per cell storage capability. The fabrication technologies of the two novel devices are fundamentally compatible with standard CMOS process

The impact of forming temperature on material and electrical characteristics of nickel silicide gate electrode

In this letter, the material and electrical characteristics of the nickel silicide (NiSi) formed at various RTA temperatures as gate electrode has been studied. By comparing various samples formed at 400 degC, 450 degC, 500 degC, and 600 degC with Vfb-EOT curves, work function and fixed charge, we found that when the RTA temperature is higher than 500 degC the interaction between the NiSi and SiO2 damage the gate dielectric (silicon dioxide) and change the effective work function of the NiSi (from 400 degC 4.47eV to 600 degC 4.64eV) by defects which is result of Ni-Si bonds. And the work function of NiSi is 4.47 plusmn 0.02 eV (formed at 400 degC, 450degC and 500degC). Finally we compared the reliability of the NiSi gate capacitor formed at 400 degC 450 degC and 500 degC, and get the conclusion that NiSi formed at 400 degC and 450 degC is stable on the silicon oxide

Study on the impact of Ge-implantation on the work function of fully silicided NiSi gate as ultra-shallow junction formed by using germanium preamorphization

In this paper the impact of Ge-implantation on the work function of fully silicided NiSi gate is investigated. C-V measurement shows that work functions of NiSi gates with and without Ge implantation vary slightly, from 4.759 eV to 4.729 eV. The increase of interface state and fixed oxide charge introduced by Ge preamorphization implantation is not observed. These results demonstrate that fully silicided NiSi gate technology can be integrated with Ge preamorphization implantation in self alignment CMOS process.