Xinkai Chen

An Energy-Efficient ASIC for Wireless Body Sensor Networks in Medical Applications

An energy-efficient application-specific integrated circuit (ASIC) featured with a work-on-demand protocol is designed for wireless body sensor networks (WBSNs) in medical applications. Dedicated for ultra-low-power wireless sensor nodes, the ASIC consists of a low-power microcontroller unit (MCU), a power-management unit (PMU), reconfigurable sensor interfaces, communication ports controlling a wireless transceiver, and an integrated passive radio-frequency (RF) receiver with energy harvesting ability. The MCU, together with the PMU, provides quite flexible communication and power-control modes for energy-efficient operations. The always-on passive RF receiver with an RF energy harvesting block offers the sensor nodes the capability of work-on-demand with zero standby power. Fabricated in standard 0.18-¿m complementary metal-oxide semiconductor technology, the ASIC occupies a die area of 2 mm × 2.5 mm. A wireless body sensor network sensor-node prototype using this ASIC only consumes < 10-nA current under the passive standby mode, and < 10 ¿A under the active standby mode, when supplied by a 3-V battery.An energy-efficient application-specific integrated circuit (ASIC) featured with a work-on-demand protocol is designed for wireless body sensor networks (WBSNs) in medical applications. Dedicated for ultra-low-power wireless sensor nodes, the ASIC consists of a low-power microcontroller unit (MCU), a power-management unit (PMU), reconfigurable sensor interfaces, communication ports controlling a wireless transceiver, and an integrated passive radio-frequency (RF) receiver with energy harvesting ability. The MCU, together with the PMU, provides quite flexible communication and power-control modes for energy-efficient operations. The always-on passive RF receiver with an RF energy harvesting block offers the sensor nodes the capability of work-on-demand with zero standby power. Fabricated in standard 0.18-¿m complementary metal-oxide semiconductor technology, the ASIC occupies a die area of 2 mm × 2.5 mm. A wireless body sensor network sensor-node prototype using this ASIC only consumes < 10-nA current under the passive standby mode, and < 10 ¿A under the active standby mode, when supplied by a 3-V battery.

A Low-Power Digital IC Design Inside the Wireless Endoscopic Capsule

This paper proposes an architecture of the wireless endoscopy system for the diagnoses of whole human digestive tract and real-time endoscopic image monitoring. The low-power digital IC design inside the wireless endoscopic capsule is discussed in detail. A very large scale integration (VLSI) architecture of three-stage clock management is applied, which can save 46% power inside the capsule compared with the design without such a low-power design. A stoppable ring crystal oscillator with minimal overhead is used in the sleep mode, which results in about 60-muW system power dissipation in sleep mode. A new image compression algorithm based on Bayer image format and its corresponding VLSI architecture are both proposed for low-power, high-data volume. Thus, 8 frames per second with 320*288 pixels can be transmitted with 2 Mb/s. The digital IC design also assures that the capsule has many flexible and useful functions for clinical application. The digital circuits were verified on field-programmable gate arrays and have been implemented in 0.18-mum CMOS process with 6.2 mW

A Wireless Capsule Endoscope System With Low-Power Controlling and Processing ASIC

This paper presents the design of a wireless capsule endoscope system. The proposed system is mainly composed of a CMOS image sensor, a RF transceiver and a low-power controlling and processing application specific integrated circuit (ASIC). Several design challenges involving system power reduction, system miniaturization and wireless wake-up method are resolved by employing optimized system architecture, integration of an area and power efficient image compression module, a power management unit (PMU) and a novel wireless wake-up subsystem with zero standby current in the ASIC design. The ASIC has been fabricated in 0.18-mum CMOS technology with a die area of 3.4 mm * 3.3 mm. The digital baseband can work under a power supply down to 0.95 V with a power dissipation of 1.3 mW. The prototype capsule based on the ASIC and a data recorder has been developed. Test result shows that proposed system architecture with local image compression lead to an average of 45% energy reduction for transmitting an image frame.This paper presents the design of a wireless capsule endoscope system. The proposed system is mainly composed of a CMOS image sensor, a RF transceiver and a low-power controlling and processing application specific integrated circuit (ASIC). Several design challenges involving system power reduction, system miniaturization and wireless wake-up method are resolved by employing optimized system architecture, integration of an area and power efficient image compression module, a power management unit (PMU) and a novel wireless wake-up subsystem with zero standby current in the ASIC design. The ASIC has been fabricated in 0.18-mum CMOS technology with a die area of 3.4 mm * 3.3 mm. The digital baseband can work under a power supply down to 0.95 V with a power dissipation of 1.3 mW. The prototype capsule based on the ASIC and a data recorder has been developed. Test result shows that proposed system architecture with local image compression lead to an average of 45% energy reduction for transmitting an image frame.

A wireless capsule endoscopic system with a low-power controlling and processing ASIC

This paper presents the design of a wireless capsule endoscopic system with a low-power controlling and processing ASIC. The system aims at several design challenges including system power reduction, system miniaturization and wireless wake-up method. These challenges are met by employing optimized system architecture, integration of an area and power efficient image compression module, a power management unit (PMU) and a novel wireless wake-up subsystem with zero standby current in the ASIC design. The ASIC has been fabricated in 0.18-mum CMOS technology, and occupies a die area of 3.4 mm*3.3 mm. The digital core can work under a power supply down to 0.95V, and the power consumption is only 1.3 mW. The wireless capsule endoscope prototype has been implemented with this ASIC.

A Low Power, Fully Pipelined JPEG-LS Encoder for Lossless Image Compression

By analyzing the features unfit for parallel computation and low power implementation, a VLSI architecture of JPEG-LS encoder for lossless image compression is proposed in this paper. It functionally consists of four parts: Mode decision module, clock controller, three linear parallel pipelines, and a two-tier data packer. Computations are organized in a fully pipelined style in these modules, so that real time data processing can be achieved. The clock management scheme with four interlaced clock domains and a dedicated clock controller is applied to ensure the bottleneck calculation, reduce the clock frequency on non-critical paths, and shut off the working clocks of idle modules, which reduces 15.7% of overall power consumption. The proposed JPEG-LS encoder with the features of low power and high processing speed, has been applied in a wireless endoscopy system.

A novel low power IC design for bi-directional digital wireless endoscopy capsule system

This paper presents a novel analog-digital mix-mode low power IC implemented in a CMOS process used for a bi-directional digital wireless endoscope capsule. The proposed system can implement the diagnoses of whole human digestive tract. It has some characterized features such as real time endoscopy image monitoring, adjustment of the view angle and focus, 3-dimension range image acquisition, and controllability of capsule movement. The architecture, specifications and characteristics of the IC are demonstrated.

An energy efficient implementation of on-demand MAC protocol in medical Wireless Body Sensor Networks

This paper presents an energy-efficient implementation of a real-time on-demand MAC protocol for medical Wireless Body Sensor Network (WBSN). Medical WBSN is focused on pervasive healthcare and medical applications, such as monitoring vital signs, making basic drug delivery, etc. The sensor nodes in the heterogeneous WBSN generally require different data rates, due to their differing functions. Additionally, because of the strict resource constraints, the sensor nodes must be ultra-low-power. Thirdly, low-rate treatment-function nodes must also “work-on-demand” to prove proper activities in the slave nodes such as stimulus and drug delivery. These three requirements cannot currently be satisfied simultaneously in commonly-used single channel implementations because the channel monitoring consumes too much power for long-term use. In the proposed implementation, a secondary channel is introduced in, which is used for channel listening only. Benefiting from the secondary channel, the node can achieve both real-time “work-on-demand” and zero idle power, by means of recovering energy from the “demand token”. An elaborated energy-harvesting RF module achieves monitoring the secondary channel. The prototype system of sensor nodes is expected for the zero-idle-power and the response time of less than 2ms.

A SoC with 3.9mW 3Mbps UHF transmitter and 240μW MCU for capsule endoscope with bidirectional communication

An ultra-low-power system-on-a-chip (SoC) for wireless capsule endoscopes has been implemented, providing bidirectional communication between the capsule and the external data logger. The SoC is composed of a programmable UHF band transceiver with 3Mbps MSK transmitting and 64kbps OOK receiving, a 1.2V MCU with a dedicated image compressor, multiple on-chip voltage regulators, and etc. The SoC can work with a power supply down to 2.5V. The 3Mbps transmitter working at 400MHz band consumes only 3.9mW power, and the MCU draws only 200μΑ current from 1.2V supply. Fabricated in 0.18μm CMOS, the SoC occupies a die area of 13.3mm2 including the I/O pads. A capsule endoscope prototype has been developed using this SoC plus an image sensor. With this SoC, the capsule endoscope can capture 512∗512 gastrointestinal images with a frame rate of up to 3 fps.

A VLSI design of sensor node for wireless image sensor network

This paper presents a single chip VLSI architecture of wireless image sensor node, which is constituted by an enhanced embedded 8051 microcontroller, a CMOS camera interface and hardware accelerators. The algorithms and control flows of the IEEE 802.15.4 MAC layer are accelerated by hardware, results in 45% less code size compared with the conventional software stack. An innovated CFA preprocessing algorithm and JPEG-LS compressing method is adopted and implemented by hardware, which has a minimal 46.3dB PSNR, an average compression ratio of about 3.0bit/pixel and an approximately 5fps at 16MHz system clock. Furthermore, low power design and techniques are employed to extend battery life, resulting in 60mW max system power consumption when the SoC is in full working mode (i.e. processor, image processing and wireless communication are active simultaneously) in 0.18µm CMOS process.

A novel compression method for wireless image sensor node

This paper presents the design of a novel compression method for wireless image sensor node. In order to meet the requirement of the wireless image sensor node, a dedicated filtering procedure is developed for raw Bayer CFA pattern. JPEG-LS encoder follows the filtering procedure to compress the data. The parallel and pipeline structure are chosen for the purpose of high throughput and real-time operation. The compression method is implemented using UMC 0.18 mum technology. The test results shown that the image with VGA (640times480) resolution and frame rate 15 fps can be achieved with the same clock frequency with the CMOS image sensor.