Xinpeng Xing

A 42 fJ/Step-FoM Two-Step VCO-Based Delta-Sigma ADC in 40 nm CMOS

A 40 MHz-BW 10 bit two-step VCO-based Delta-Sigma ADC is presented. With the open-loop structure and highly digital building blocks, a robust performance, high bandwidth and high power efficiency are achieved. The nonlinearities of the coarse and the fine VCO-based quantizers are mitigated by distortion cancellation and voltage swing reduction schemes respectively. Because of the intrinsic DEM of the VCO-based quantizer output, the matching requirement of the DAC cells is greatly relaxed. The experimental results in 40 nm CMOS show that, with 1.6 GHz sampling frequency, the proposed ADC reaches 59.5 dB SNDR and 67.7 dB SFDR for 40 MHz bandwidth. The power consumption is only 2.57 mW under 0.9 V power supply, corresponding the best FoM (42 fJ/step) among high bandwidth ( 20 MHz) DS ADCs.

Calibration of DAC Mismatch Errors in

We present an offline calibration procedure to correct the nonlinearity due element mismatch in the digital-to-analog converter (DAC) of a multibit ΣΔ-modulation A/D converter. The calibration uses a single measurement on a sinusoidal input signal, from which the DAC errors can be estimated. The main quality of the calibration method is that it can be implemented completely in the digital domain (or in software) and does not intervene in any way in the analog modulator circuit. This way, the technique is a powerful tool for verifying and debugging designs. Due to the simplicity of the method, it may be also a viable approach for factory calibration.

\Sigma\Delta

This paper presents the modeling and design consideration of a time-based ADC architecture that uses VCOs in a high-linearity, 2nd-order noise-shaping delta-sigma ADC. Instead of driving the VCO by a continuous analog signal, which suffers from the nonlinearity problem of the VCO gain, the VCO is driven in an intrinsically linear way, by a time-domain PWM signal. The two discrete levels of the PWM waveform define only two operating points of the VCO, therefore guaranteeing linearity. In addition, the phase quantization error between two consecutive samples is generated by a phase detector and processed by a second VCO. Together with the output of the first VCO, a MASH 1-1 2nd-order noise-shaping VCO-based time-domain delta-sigma converter is obtained. Fabricated in 90 nm CMOS technology, the SFDR is larger than 67 dB without any calibration for a 20 MHz bandwidth.

ADCs Based on a Sine-Wave Measurement

This brief presents a nonlinearity-cancelation technique in a 0-2 MASH voltage-controlled oscillator (VCO)-based delta-sigma (ΔΣ) analog-to-digital converter (ADC), where the VCOs distortion is substantially mitigated in a power-efficient way. A dual-input VCO-based quantizer topology is also proposed to implement a low-power multiple-input adder and integrator, with nox penalty in terms of nonlinearity. Fabricated in a 40-nm complementary metal-oxide-semiconductor process, a proof-of- concept 0-2 MASH 12-bit ADC prototype achieves a 66.8-dB signal-to-noise and distortion ratio with a 40-MHz bandwidth (BW) and consumes only 4.98 mW. This result extends the figure of merit of the state-of-the-art high-BW (ΔΣ) ADCs to 35 fJ/step.

Design of an intrinsically-linear double-VCO-based ADC with 2 nd -order noise shaping

A two-step open-loop VCO-based ADC with 1st-order noise shaping and intrinsic nonlinearity mitigation is presented. With the open-loop structure and highly digital building blocks, a robust performance, high bandwidth and high efficiency is achieved. The nonlinearities of the VCOs in the coarse and fine quantizers are improved by a distortion cancellation and a voltage swing reduction scheme respectively. Because of the intrinsic DEM of the VCO-based quantizer output, the matching requirement of the DAC cells is greatly relaxed. The design is implemented in 40nm CMOS and shows that, with 1.6GHz sampling frequency, the two-step VCO-based ADC reaches 40MHz bandwidth, 59.5dB SNDR and 67.7dB SFDR. The power consumption is only 2.57mW, corresponding to an excellent FoM of 42fJ/step.

A 40-MHz Bandwidth 0–2 MASH VCO-Based Delta-Sigma ADC With 35-fJ/Step FoM

This paper presents a nonlinearity cancellation technique in a closed-loop two-step VCO-based ADC, where the VCOs distortion is substantially mitigated in a robust manner. A dual-input VCO-based quantizer topology is proposed to realize a low-power multi-input adder, with no penalty in terms of nonlinearity. Fabricated in a 40nm CMOS process, the prototype two-step 12-bit ADC achieves 68.7dB/66.8dB SNR/SNDR with a 40MHz bandwidth and consumes only 4.98mW. This corresponds to an excellent FoM of 35fJ/step.

A 40MHz-BW two-step open-loop VCO-based ADC with 42fJ/step FoM in 40nm CMOS

With CMOS technology scaling, the analog and mixed-signal circuits face more and more design challenges and suffer a lot in accuracy. At the same time, digital circuits benefit from technology scaling in terms of improved timing accuracy and reduced power consumption.

A 40MHz-BW 35fJ/step-FoM nonlinearity-cancelling two-step ADC with dual-input VCO-based quantizer

Scaling friendly in the light of the reducing voltage headroom and increasing time resolution of the nanometer CMOS technology, VCO-based quantizers have been exploited in CT \(\varDelta \varSigma \) ADCs.

VCO-Based ADCs

Ever higher data rates in both wireless and wireline communications lead to an ongoing increase in signal bandwidths. In receiver chains, the variable gain amplifiers (VGAs) and the automatic gain control loops (AGCs) can be relaxed or even be removed if the dynamic range (DR) of the following analog-digital converter (ADC) is high enough, simplifying the analog front-end by (Silva et al. IEEE J Solid-State Circuits 42(5):1076–1089 (2007), [1]).

Fully-VCO-Based High-Order \(\varDelta \varSigma \) ADC

DSM ADCs trade off speed for accuracy by using oversampling and noise shaping techniques. Compared to discrete-time (DT) DSMs, usually continuous-time (CT) DSMs are applied for higher-bandwidth and lower-accuracy A/D conversions.