Xinwang Zhang

A 0.1–5GHz flexible SDR receiver in 65nm CMOS

A 0.1-5GHz flexible software-defined radio (SDR) receiver is presented with three RF front-end paths (Main/Sub/HR paths). Main path and sub path can reject out-of-band blockers and harmonic interferences, and feature low NF and high linearity, respectively. Harmonic rejection (HR) path can effectively reject the harmonic interferences with simple calibration mechanism. Dual feedback LNA, class-AB Op-Amp with miller feed-forward compensation and quasi-floating gate (QFG) techniques, reconfigurable continuous-time (CT) low pass (LP) and complex band pass (CBP) sigma-delta ADC are proposed. This chip has been implemented in 65nm CMOS with 9.6-47.4mA current consumption from 1.2V voltage supply and a core chip area of 5.4mm2. The receiver main path achieves 3.8dB NF, +5dBm/+5dBm IB-IIP3/OB-IIP3 as well as +58dBm IIP2. The sub path achieves +10dBm/+18dBm IB-IIP3/OB-IIP3 as well as +61dBm IIP2. And it offers RF filtering with 10dB rejection at 10MHz offset. The HR path achieves +13dBm/+14dBm IB-IIP3/OB-IIP3 and >54/56dB 3rd/5th-order harmonic rejection with 30-40dB rejection improvement by calibration.

Dual-mode 10MHz BW 4.8/6.3mW reconfigurable lowpass/complex bandpass CT ΣΔ modulator with 65.8/74.2dB DR for a zero/low-IF SDR receiver

A dual-mode wideband reconfigurable lowpass /complex bandpass continuous-time sigma-delta (LP/CBP CT ΣΔ) modulator with digitally-assisting integrated in a zero/ low-IF SDR receiver is presented. The proposed modulator is capable of switching in either 3rd-order LP or 2nd-order CBP with 10MHz bandwidth (BW) in each mode. The power-efficient amplifiers in active-RC integrators are implemented with active feedforward and anti-pole-splitting compensation schemes. The 2-bit digitally-switched current-steering DAC with gate-leakage compensation is proposed to cover the current variation in LP/CBP mode and solve the unavoidable gate-leakage issue in deep submicron CMOS. Fabricated in 65nm CMOS, the modulator achieves 65.8dB DR, 62.2dB peak SNDR in LP 10MHz BW mode and 74.2dB DR, 63.9dB SNDR across 10MHz signal-band with center frequency of 6MHz in CBP mode, occupying a core area of 0.39mm2. Powered by a 1.2-V supply, the effective power consumption is only 4.8 and 6.3mW in LP and CBP mode respectively, resulting in measured FoMs of 0.23 and 0.25pJ/conversion.

A 0.1∼4GHz receiver and 0.1∼6GHz transmitter with reconfigurable 10∼100MHz signal bandwidth in 65nm CMOS

A 8.12mm2 0.1-4GHz receiver and 0.1~6GHz transmitter with reconfigurable 10~100MHz signal bandwidth in 65nm CMOS is presented. Rx features two single-ended LNAs in parallel, passive current down-conversion with 25% duty-cycle LOs, 5th/7th-order reconfigurable baseband filtering and IIP2/frequency tuning/IQ calibration. It achieves NF of 3~8dB over 0.1-4GHz and 21mA current consumption for 2.3GHz LTE with 20MHz signal bandwidth. Fully-integrated Tx features reconfigurable PPAs with transformer differential-single-ended conversion output, a low-noise sub-path and high dynamic range main-path as well as LO leakage and image rejection calibration. It achieves 1.7% EVM for 1.8GHz WCDMA with 1.5dBm output power, -31/-51 ACLR1/ACLR2 for 2.3GHz LTE with 20MHz bandwidth at 3dBm output power, <;-42dBc LO feedthrough and >;51dBc image rejection.

An LP/CBP reconfigurable analog baseband circuit for software-defined radio receivers in 65nm CMOS

A low pass (LP) and complex band pass (CBP) reconfigurable analog baseband circuit for software-defined radio (SDR) receivers is presented. It achieves 1-15MHz LP bandwidth, 2-8MHz CBP bandwidth and 0-36dB gain range with 1dB step. Nulling-resistor Miller feed-forward (NRMFF) differential-mode compensation, passive left half-plane (LHP) zero common-mode compensation and Quasi-Floating Gate (QFG) technique are proposed to improve the high frequency performance and driving capability of the embedded fully differential operational amplifier (Op-Amp). The analog baseband circuit has been implemented in 65nm CMOS. It achieves 15.2dBm/27.1dBm IB/OB-IIP3, -2dBm IP1dB and 71dBm IIP2 while consuming 3.6-9.1mW from a 1.2V power supply and 0.75mm2 chip area.

A 0.1–1.5 GHz Harmonic Rejection Receiver Front-End With Phase Ambiguity Correction, Vector Gain Calibration and Blocker-Resilient TIA

A 0.1-1.5 GHz harmonic rejection (HR) receiver front-end is presented. A flexible HR mixer is proposed to correct phase ambiguity and a vector gain calibration is used to eliminate the gain/phase mismatch and improve the HR ratio. With the proposed hybrid 8-phase LO generator, the highest oscillation frequency of the frequency synthesizer is reduced from four times to twice of the highest operation frequency. The power-scalable Class-AB fully-differential opamp with Miller feed-forward compensation and quasi-floating gate (QFG) technique is proposed to implement the low power blocker-resilient TIA. The HR receiver has been implemented in 65 nm CMOS. With 1.8 mm2 core chip area and 5.4-24.5 mA current consumption from a 1.2 V power supply, the receiver achieves 85 dB conversion gain, 4.3 dB NF, +13 dBm/ +14 dBm IB/OB-IIP3, >54/56 dB HR3/HR5 (30-40 dB improvement with the vector gain calibration), and 2.3% EVM for 32QAM modulation.

A 0.1–1.5GHz harmonic rejection receiver front-end with hybrid 8 phase LO generator, phase ambiguity correction and vector gain calibration

A 0.1-1.5GHz harmonic rejection (HR) receiver front-end is presented. A flexible HR mixer is proposed to correct phase ambiguity, and a vector gain calibration is used to eliminate the gain/phase mismatch and improve the HR ratio. With the proposed hybrid 8 phase local oscillating (LO) generator, the highest carrier frequency from the frequency synthesizer is only twice of the desired LO frequency. The HR receiver has been implemented in 65nm CMOS. With 1.8mm2 core chip area and 5.4-24.5mA current consumption from a 1.2V power supply, the receiver achieves 85dB conversion gain, 4.3dB NF, +13dBm/+14dBm IB/OB-IIP3, >54/56 dB HR3/HR5 with 30-40dB improvement by calibration, and 2.3% EVM with 32QAM modulation signal.

An Interference-Robust Reconfigurable Receiver With Automatic Frequency-Calibrated LNA in 65-nm CMOS

An interference-robust reconfigurable receiver in 65-nm CMOS is presented. The front end is split into a low-band (LB) RF path (0.1–1.5 GHz) and a high-band (HB) RF path (1–5 GHz). By utilizing a harmonic recombination technique, the LB path could reject the third /fifth-order harmonic interferences. A tunable narrowband dual-feedback common-gate low-noise amplifier (LNA) with

A 1.0–5.0GHz tunable LNA with automatic frequency calibration in 65 nm CMOS

LC

A 0.5–30GHz wideband differential CMOS T/R switch with independent bias and leakage cancellation techniques

resonant load provides second-order bandpass filtering to reject the harmonic interferences in the HB path. The RF high-Q bandpass filtering based on the voltage-mode passive mixer and the current-mode low-pass filter in the analog baseband improves the receiver’s resilience to out-of-band interferences. A novel power-detection-based automatic frequency calibration technique is proposed to calibrate the operating frequency of the LNA in the HB path and overcome the effects of process, voltage, and temperature variations. The presented receiver has been implemented in a 65-nm CMOS and consumes 20–76-mW power from 1.2-V power supplies, with a core die area of 5 mm2. The measured results show that the receiver can tolerate −5-dBm interference with 16-dB noise figure (NF) and achieve 95–105-dB maximum conversion gain and 1.7–8-dB NF over 0.1–5 GHz. It also achieves an average harmonic rejection (HR3)/HR5 of 61/68-dB, +7.1/+14.4 dBm in-band/out-of-band input third-order intercept point (OB-IIP3), +71.2-dBm OB-IIP2, and 58.1-dB-image rejection, after the digitally assisted calibrations. The system-level measurements show that the presented receiver achieves 2.1% error vector magnitude (EVM) for 850-MHz Global System for Mobile Communication signals and 5% EVM for band 42 time division duplexing-local thermal equilibrium (LTE) signals, respectively.

A 0.1–6.0-GHz Dual-Path SDR Transmitter Supporting Intraband Carrier Aggregation in 65-nm CMOS

A 1.0-5.0 GHz tunable low-noise amplifier (LNA) in 65 nm is presented, which employs dual feedback common gate (CG) topology to reduce the noise figure (NF) and out-of-band interference. The amplitude-detection-based automatic frequency calibration technique is proposed to overcome the effects of the process variation with little extra cost. The measured average frequency error after the calibration is less than 4.4 MHz. The proposed dual feedback CG-LNA achieves the power gain of 19~26 dB. The input matching S11 is -18 dB~-5 dB, and the NF is 2.4~3.8 dB. The chip consumes 10.06 mA from one 1.2 V power supply, with 0.7 mm2 die area consumption.