Yanqiang Gao

A 0.1–5.0 GHz Reconfigurable Transmitter With Dual-Mode Power Amplifier and Digitally-Assisted Self-Calibration for Private Network Communications

A 0.1-5.0 GHz 65 nm CMOS reconfigurable transmitter for private network wireless communications is presented. The transmitter integrates a 0.1-1.5 GHz high-efficiency dual-mode power amplifier to support low-cost narrowband applications and a 0.45-5.0 GHz efficiency-optimized pre-power amplifier to support high-performance wideband applications. A wideband PLL frequency synthesizer, DACs with reconfigurable sampling rate and the reconfigurable digital baseband processing with standard JESD207 interface are all included to implement the highly-integrated transmitter. Specifically, with the proposed digitally-assisted self-calibration technique for LO leakage and image rejection, the transmitter achieves 52 dBc LO leakage and >53 dBc image rejection ratio (IRR), showing 20 dB and 30 dB improvement compared with the un-calibrated cases, respectively. The system verifications have demonstrated an EVM of 1.7% for 905 MHz EDGE with 19.5 dBm output power, and an EVM of 3.2% for LTE Band42 with 5.5 dBm output power. This proposed transmitter has achieved the comparable or even better performance in linearity, noise floor and power consumption compared with the state-of-the-art reconfigurable transmitters.

A 0.1–5GHz flexible SDR receiver in 65nm CMOS

A 0.1-5GHz flexible software-defined radio (SDR) receiver is presented with three RF front-end paths (Main/Sub/HR paths). Main path and sub path can reject out-of-band blockers and harmonic interferences, and feature low NF and high linearity, respectively. Harmonic rejection (HR) path can effectively reject the harmonic interferences with simple calibration mechanism. Dual feedback LNA, class-AB Op-Amp with miller feed-forward compensation and quasi-floating gate (QFG) techniques, reconfigurable continuous-time (CT) low pass (LP) and complex band pass (CBP) sigma-delta ADC are proposed. This chip has been implemented in 65nm CMOS with 9.6-47.4mA current consumption from 1.2V voltage supply and a core chip area of 5.4mm2. The receiver main path achieves 3.8dB NF, +5dBm/+5dBm IB-IIP3/OB-IIP3 as well as +58dBm IIP2. The sub path achieves +10dBm/+18dBm IB-IIP3/OB-IIP3 as well as +61dBm IIP2. And it offers RF filtering with 10dB rejection at 10MHz offset. The HR path achieves +13dBm/+14dBm IB-IIP3/OB-IIP3 and >54/56dB 3rd/5th-order harmonic rejection with 30-40dB rejection improvement by calibration.

A 0.1–5.0GHz self-calibrated SDR transmitter with −62.6dBc CIM3 in 65nm CMOS

A 0.1-5.0GHz self-calibrated SDR transmitter is presented. A complete self-calibration scheme is proposed to alleviate non-ideal effects, including RF operation frequency deviation, output power control, LO leakage and image rejection. A power mixer front-end and a V-I converter with 3rd-order nonlinearity cancellation are introduced to achieve -62.6dBc CIM3 at 5.3dBm output power in LTE band42. A Class-AB/F dual-mode PA is integrated for narrowband applications. With the self-calibration, the transmitter has obtained good robustness in RF operation frequency self-tuning, LO leakage and image rejection performance over 0.1-5.0GHz, and achieved 24.5dBm Pout with 0.7% EVM, 20dBm Pout with 1.6% EVM, 6.2dBm Pout with 2.1% EVM for GSM/EDGE/LTE signals, respectively.

An Interference-Robust Reconfigurable Receiver With Automatic Frequency-Calibrated LNA in 65-nm CMOS

An interference-robust reconfigurable receiver in 65-nm CMOS is presented. The front end is split into a low-band (LB) RF path (0.1–1.5 GHz) and a high-band (HB) RF path (1–5 GHz). By utilizing a harmonic recombination technique, the LB path could reject the third /fifth-order harmonic interferences. A tunable narrowband dual-feedback common-gate low-noise amplifier (LNA) with

A reconfigurable digital intermediate frequency module for software defined radio transmitters

LC

The Investigation of Size Effect for Dislocation Starvation Mechanism UNDER Cu Single‐Crystal Micro‐Pillar Compression

resonant load provides second-order bandpass filtering to reject the harmonic interferences in the HB path. The RF high-Q bandpass filtering based on the voltage-mode passive mixer and the current-mode low-pass filter in the analog baseband improves the receiver’s resilience to out-of-band interferences. A novel power-detection-based automatic frequency calibration technique is proposed to calibrate the operating frequency of the LNA in the HB path and overcome the effects of process, voltage, and temperature variations. The presented receiver has been implemented in a 65-nm CMOS and consumes 20–76-mW power from 1.2-V power supplies, with a core die area of 5 mm2. The measured results show that the receiver can tolerate −5-dBm interference with 16-dB noise figure (NF) and achieve 95–105-dB maximum conversion gain and 1.7–8-dB NF over 0.1–5 GHz. It also achieves an average harmonic rejection (HR3)/HR5 of 61/68-dB, +7.1/+14.4 dBm in-band/out-of-band input third-order intercept point (OB-IIP3), +71.2-dBm OB-IIP2, and 58.1-dB-image rejection, after the digitally assisted calibrations. The system-level measurements show that the presented receiver achieves 2.1% error vector magnitude (EVM) for 850-MHz Global System for Mobile Communication signals and 5% EVM for band 42 time division duplexing-local thermal equilibrium (LTE) signals, respectively.

Cyclic plastic behavior analysis based on the micromorphic mixed hardening plasticity model

A multi-mode reconfigurable digital intermediate frequency (IF) module for software defined radio (SDR) transmitters is presented. It supports variable input sample rate from 7kHz to 30.72MHz, and variable signal bandwidth from 5kHz to 20MHz. Its output sample rate is 80MHz or 160MHz.The digital IF module consists of 7 half-band filters, a digital up converter (DUC) and 4 FIR filters. Each stage can be turned off separately. The 10-bit output signal to noise and distortion ratio (SNDR) is above 54.5dB, while the 12-bit input signal SNDR is 60dB.This digital IF module supports both traditional narrowband industry-specific network and LTE cluster communication applications.

Wedge indentation of a thin film on a substrate based on micromorphic plasticity

The stress‐strain response of Cu single‐crystal compression micro‐pillar containing initial dislocation networks has been investigated in this paper by three‐dimensional discrete dislocation dynamics simulations. It demonstrates that the stress‐strain curves can be divided into three types of hardening curves corresponding to increase micro‐pillar sizes: the three‐stage exhaustion hardening curve, multi‐stage mixed hardening curve and two‐stage conventional forest hardening curve. The characteristic dimensions of the pillars have been determined to differentiate three types of hardening curves.