Xiucheng Hao

An 89 μW MICS/ISM band receiver for ultra-low-power applications

This paper presents a MICS/ISM band receiver for ultra-low-power applications with a passive RF front-end. A shunt passive mixer along with low input capacitance amplifiers is introduced to decrease the large load capacitor and minimize power consumption of the Local Oscillator (LO) buffers without significant noise figure (NF) degradation. Measurement results show that the receiver consumes 89 μW from 1 V supply voltage with a NF of 7.5 dB and a voltage gain of 47.6 dB. S11<−10 dB can be achieved at the frequency range of 400–450 MHz. The baseband filter achieves a third order filtering response with 1.5 MHz bandwidth. Implemented in a 130 nm CMOS technology, the receiver occupies an active area of only 0.137 mm2.

A 93.7% peak efficiency DC-DC buck converter with all-pass network based passive level shifter in 55 nm CMOS

This paper proposes a DC-DC buck converter with all-pass network based passive level shifter in 55nm standard CMOS process, for battery powered portable applications. In order to handle high battery voltages in this advanced standard CMOS process, a passive level shifter based on all-pass network is applied for gate oxide protection. Drain extension is proposed to obtain high breakdown voltage of active region. The proposed buck converter with the passive level shifter works in DCM operation as its load current varies from 0.1–10mA. The buck converter achieves a peak efficiency of 93.7% and 83.8% at 10mA load current, with a supply voltage of 1.8V and 3.7V, respectively.

A 7.9 fJ/conversion-step 10-bit 125 MS/s SAR ADC with simplified power-efficient digital control logic

This paper presents a 7.9 fJ/conversion-step 10-bit 125 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) on the basis of a monotonic capacitor switching procedure. Simplified power-efficient digital control logic, multi-layer sandwich capacitor structure and high-speed level-shift bootstrapped sampling-and-holding (S/H) blocks are employed to achieve high performance with low power consumption. The prototype is implemented in 55 nm standard CMOS process, occupying an active area of 0.18 mm × 0.20 mm. Post simulation results show that an SNDR of 54.01 dB and an ENOB of 8.7 bit can be achieved by consuming 0.41 mW of the ADC core from a 1.2 V supply, and a figure of merit (FOM) of 7.9 fJ/conversion-step.

A hysteretic buck DC-DC converter achieving 90% peak efficiency with light-load current of 0.1–10 mA

A buck DC-DC converter with very high light load efficiency is presented in this paper. It introduces hysteretic control when the large output ripple problem is not critical, especially in light-load condition. Moreover, a fast-response zero current detector (ZCD) is adopted to make the converter work in discontinuous conduction mode (DCM). Due to hysteretic control extremely simplified the control circuits, the converter is divided into two independent loops, which further simplifies the optimization of power consumption. The proposed converter is fabricated in a standard 55 nm CMOS process. It converts 1.8–2.5 V battery voltage into a stable output voltage of 1 V, and offers 100µA to 10mA light-load current output. The hysteretic converter achieves peak efficiency of 88.5% and 90%, with a supply voltage of 2.5 V and 1.8 V, respectively.