Yongan Zheng

A wide band CMOS radio frequency RMS power detector with 42-dB dynamic range

A wide band radio frequency (RF) root-mean-square (RMS) power detector (PD) is presented in this paper. A CMOS rectifier with unbalanced source-coupled pairs and auxiliary capacitors is utilized to constitute the reverse received signal strength indicator (reverse-RSSI) architecture as proposed power detector with operating frequency from 300 MHz to 10 GHz. The auxiliary capacitors are introduced to improve linearity at high input power dramatically. The power detector can be connected to power amplifier without directional coupler due to the capacitor attenuation array. Simulation results show that the maximum detection power is as high as +30 dBm and dynamic range reaches more than 42 dB with ±1 dB error. The proposed power detector is implemented in a standard 180nm CMOS process with 0.113 mm2 core area. The supply voltage is 3.3 V, and its static power consumption is 0.55 mW.

Human body channel energy harvesting scheme with −22.5 dBm sensitivity 25.87% efficiency threshold-compensated rectifier

A novel human body channel (HBC) energy harvesting scheme for body sensor networks (BSNs) is proposed in this paper. Human body channel is utilized innovatively as energy transmission medium to reduce the transmission loss dramatically and eliminate influence of shadow effect. Further, a high sensitivity and efficiency rectifier is presented by introducing an effective threshold compensation circuit. Experimental results of the energy harvesting scheme show that it can supply 2-μW power typically at -5 dBm transmitted power and up to 19.5-μW at +7 dBm transmitted power by 30 cm distance of human body channel. The sensitivity of the proposed rectifier is -22.5 dBm with 1-V output voltage. When offering 5-μA output current, the rectifier can achieve 25.87% efficiency. The rectifier is implemented in a standard 0.18-μm CMOS process and operating frequency is 145 MHz.

A 0.5–2 GHz high frequency selectivity RF front-end with series N-path filter

This paper presents a 0.5-2GHz RF front-end with Series N-path Filter. With series 8-path filter applied, an ultimate rejection larger than 46 dB with 30 dB out-of-band rejection at 50 MHz offset is achieved. Dynamic power consumption is saved due to small filter switch size compared with parallel structures. Utilizing a tunable narrow band LNA in front of series N-path filter, 3rd harmonic rejection exceeding 54 dB with robust to process variation is realized. These techniques improve the front-ends adjacent and far-end frequency selectivity in RF domain, relaxing mixers linearity design pressure. Implemented in 65 nm CMOS process, the frontend achieves a NF of 2.6-5.7 dB and maximum gain of 46-60 dB at 0.5-2 GHz, consuming 18-26 mW from 1.2 V voltage supply and occupies an area of 0.56 mm2.

A single-poly EEPROM with low leakage charge pump and peripheral circuits for passive RFID tag in a standard CMOS technology

A complete single-poly 2k-bit EEPROM solution including memory cells and peripheral circuits is presented and embedded into a passive RFID tag using a 0.18-μm standard CMOS technology. A charge pump with a Diode-C all-pass network and peripheral circuits without static current are proposed to reduce power consumption. A three-transistor memory cell is adopted for CMOS-compatibility, low operation voltage, and low complexity of drivers. The proposed EERPOM occupies an active area of 0.21mm2. The leakage current during read operation is 36 nA from 1-V supply, while the static current during write operation is 1.3 μA from 1.8-V supply.

A 93.7% peak efficiency DC-DC buck converter with all-pass network based passive level shifter in 55 nm CMOS

This paper proposes a DC-DC buck converter with all-pass network based passive level shifter in 55nm standard CMOS process, for battery powered portable applications. In order to handle high battery voltages in this advanced standard CMOS process, a passive level shifter based on all-pass network is applied for gate oxide protection. Drain extension is proposed to obtain high breakdown voltage of active region. The proposed buck converter with the passive level shifter works in DCM operation as its load current varies from 0.1–10mA. The buck converter achieves a peak efficiency of 93.7% and 83.8% at 10mA load current, with a supply voltage of 1.8V and 3.7V, respectively.

A 51-nW 32.7-kHz CMOS relaxation oscillator with half-period pre-charge compensation scheme for ultra-low power systems

This paper presents a temperature and supply voltage variation-tolerant CMOS relaxation oscillator which is suitable for ultra-low power systems. A low-power low-cost half-period pre-charge compensation scheme is proposed to eliminate influences of the delay of the comparator and the RS latch on the frequency stability of the relaxation oscillator. In a clock period consisting of four working stages including normal charge, discharge, pre-charge and hold stage, the threshold voltage of comparators is adjusted dynamically. A 32.7-kHz relaxation oscillator with the proposed half-period pre-charge compensation scheme is implemented in a TSMC 0.18-μm CMOS process, occupying a silicon area of 0.048 mm2. Simulation results show that the proposed relaxation oscillator consumes 51-nW at room temperature from 0.6-V power supply, and temperature stability of 43.1 ppm/°C from -55 °C to 125 °C and ±0.60% frequency variation with supply voltage from 0.5 V to 1.0 V are achieved.

A low power self-turnoff program method for one-time programmable memory

A novel self-turnoff control circuit for program process of one-time programmable (OTP) cell is proposed. Utilizing the current turnoff technology after the breakdown of OTP cell, it lowers the power consumption efficiently compared with traditional structures without turnoff mechanism. In addition, an additional delay circuit is also attached to the self-turnoff circuit to ensure the complete breakdown of OTP cell. The simulation results show that the average power consumption of proposed circuit decreases to about 3nA in the whole program process.

An ultra low power digital processor for Chinese UHF RFID transponder

An ultra low power digital baseband processor for passive UHF RFID tag which is compatible with the protocol of Chinese local standard (840-845 MHz and 920-925 MHz) is presented in this paper. A highly reused register bank and a low-cost sort algorithm are proposed to minimize the power consumption and several other low power techniques are adopted, including low supply voltage, clock gating, and minimum operation frequency. The processor is fabricated in SMIC 0.18 um standard CMOS process and consumes 358 nA at 0.6 V voltage supply according to measured results and occupies only 0.1 mm2 area.

SAW-less GNSS front-end amplifier with 80.4-dB GSM blocker suppression using CMOS directional coupler notch filter

This paper presents a SAW-less GNSS front-end amplifier with GSM blocker suppression using CMOS directional coupler notch filter. The front-end amplifier is aimed at the GNSS receiver integrated in cellular phones. Based on our proposed CMOS stacked spiral-coupled (SSC) directional coupler working at the frequency of 900MHz as notch filter, the front end amplifier achieves a NF of 1.7dB and a 80.4-dB suppression of the GSM blocker while provides signal gain of 38.6-dB for the GPS L1-band signal.