Zhixiong Ren

Wideband CMOS mixer using differential circuit transconductance linearization technique

In this paper, a highly linear wideband down-conversion mixer using multiple gated transistor technique (MGTR) is presented. The mixer is designed and fabricated in 0.18-μm 1P6M RF CMOS process. To achieve high IIP3 performance, the MGTR technique is implemented both in the transconductance stage and the output buffer. An achievement of 0.6~7.2 dBm IIP3 operating in the frequency band from 0.045 to 2.5 GHz is attained without significant degradation of gain and noise performance. The post simulation result has indicated a conversion gain of 5.8~8.6dB, a low noise figure of 7.4~9.1dB. The preliminary measured result shows good IF matching (S parameter at the output buffer) of -25.6~-9.1dB. The whole mixer has a compact die area of 0.093 mm2 and a current consumption of 9.1mA under 1.8-V supply voltage.

A 2.45-GHz W-level output power CMOS power amplifier with adaptive bias and integrated diode linearizer

A high-linearity CMOS power amplifier (PA) operating at 2.45GHz for WLAN applications with adaptive bias and an integrated diode linearizer is presented. The PA adopts adaptive bias scheme to adjust the gate bias voltage of power transistors by tracking the output power of the first diver amplifier for efficiency enhancement. Diode-connected MOS transistor is used to compensate the nonlinearity of input capacitance ( C gs ) of power transistors for linearity improvement. The simulation results demonstrate a gain of 33.2dB, a maximum output power of 30.7dBm with 29% of peak power added efficiency (PAE) and -30dBc third-order intermodulation (IMD3) product at 26.4dBm output power, reaching to excellent tradeoffs between efficiency and linearity.

On-chip transformer using multipath technique with arithmetic-progression step sub-path width

A novel on-chip transformer architecture using multipath technique is presented. The newly proposed arithmetic-progression step sub-path width method is used to lower the current-crowding effect induced by the difference between the length of inner sub-path and that of outer sub-path. Full-wave electromagnetic simulated and measured results confirm the better performance of the proposed transformers than the conventional ones. These transformers will be useful in designing high-performance CMOS RF integrated circuits for wireless applications.

0.05–2.5GHz wideband RF front-end exploiting noise cancellation and multi-gated transistors

A wideband receiver RF front-end, including a noise cancellation low-noise amplifier (LNA) and quadrature active mixers with multi-gated transistors (MGTR), is presented in this paper. The proposed front-end was fabricated in 180-nm CMOS technology, covering the input frequency range of 0.05 to 2.5 GHz and IF frequency of 0.3 to 20 MHz. It achieves conversion gain of 22.2-30.8 dB, double-sideband noise figure (NF) of 2.7-4.5 dB and input-referred third-order intercept point (HP3) of -17.7 dBm. The chip core draws 22 mA from a 1.8V supply with a die area of 1.36 mm2.

A +33dBm 1.9 GHz linear CMOS power amplifier with MOS-level linearizers

A 1.9GHz linear CMOS power amplifier (PA) using a newly proposed power combiner for higher output power is presented. The PA adopts MOS-level linearizers including the multiple gated transistors (MGTR) and PMOS compensation to reduce the non-linearity induced by the gm3 and Cgs, which are the dominant harmonic distortion sources. The schematic simulation results demonstrate a gain of 28.9dB, a maximum output power of 33dBm with 34.27% of peak power added efficiency (PAE) and -25dBc IMD3 at 26dBm output power, reaching to excellent tradeoffs between efficiency and linearity.