Fangxu Lv

A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS

This paper presents a 5-50 Gb/s quarter-rate transmitter with a 4-tap feed-forward equalization (FFE) based on multiple-multiplexer (MUX). A bandwidth enhanced 4:1 MUX with the capability of eliminating charge-sharing effect is proposed to increase the maximum operating speed. To produce the quarter-rate parallel data streams with appropriate delays, a compact latch array associated with an interleaved-retiming technique is designed. Implemented in 65 nm CMOS technology, the transmitter occupying an area of 0.6 mm2 achieves a maximum data rate of 50 Gb/s with an energy efficiency of 3.1 pJ/bit.

A power scalable 2–10 Gb/s PI-based clock data recovery for multilane applications

Abstract This paper presents a power scalable clock data recovery (CDR) suitable for multilane and multirate applications. To make the power consumption scale with the data rate and guarantee appropriate edge overlaps for the phase interpolation, a delay-locked loop-based global biasing strategy is proposed to automatically adjust the bandwidth of the current-mode logic buffers and phase interpolator (PI). The I, Q clocks are generated by a local clock conditioner, which employs an open-loop voltage-controlled delay line to produce the evenly spaced multiple phases and adopts a two-stage timing averaging to correct the duty cycle distortion and I, Q mismatch. Additionally, a phase-compensating technique is adopted in the PI to optimize its linearity. Implemented in a 65-nm CMOS process with an area occupation of 0.12 mm2, the presented CDR can operate from 2 to 10 Gb/s with a scalable power consumption from 11 to 42 mW. When it operates at 10 Gb/s, the maximum tolerable amplitude of the sinusoidal jitter at 50 MHz is 0.52 UIpp, and the total jitter of the recovered clock is 16.6 ps at a BER of 1e-12.

A 2-40 Gb/s PAM4/NRZ dual-mode wireline transmitter with 4:1 MUX in 65-nm CMOS

This paper presents a 2-40 Gb/s dual-mode wireline transmitter supporting the four-level pulse amplitude modulation (PAM4) and non-return-to-zero (NRZ) modulation with a multiplexer (MUX)-based two-tap feed-forward equalizer (FFE). An edge-acceleration technique is proposed for the 4:1 MUX to increase the bandwidth. By utilizing a dedicated cascode current source, the output swing can achieve 900 mV with a level deviation of only 0.12% for PAM4. Fabricated in a 65-nm CMOS process, the transmitter consumes 117 mW and 89 mW at 40 Gb/s in PAM4 and NRZ at 1.2 V supply.

A 40–80 Gb/s PAM4 wireline transmitter in 65nm CMOS technology

This paper presents a 40–80 Gb/s quarter rate PAM4 wireline transmitter. The transmitter incorporates a 2-tap feed-forward equalizer (FFE) based on multiple-multiplex (MUX) and a parallel PRBS7 generator. The transmitter is achieved in 65nm CMOS technology and supplied with 1.2V. The simulation results show that the proposed transmitter can work at 40–80 Gb/s with 4-level pulse amplitude modulation (PAM4) and consumes 173mW at 80 Gb/s.

A 10 GHz 56 fs rms -integrated-jitter and −247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS

This paper presents a low jitter ring-VCO based injection-locked clock multiplier (RILCM) with a phase-shift detection based hybrid frequency tracking loop (FTL). A full-swing pseudo-differential delay cell (FS-PDDC) is proposed to lower the device noise to phase noise conversion. To obtain high operation speed, high detection accuracy, and low output disturbance, a compact timing-adjusted phase detector (TPD) tightly combining with a well-matched charge pump (CP) is designed. Additionally, a lock-loss detection and lock recovery (LLD-LR) scheme is devised to equip the RILCM with a similar lock-acquisition ability to conventional PLL, thus excluding the initial frequency setup aid and preventing potential lock loss. Implemented in 65 nm CMOS, the RILCM occupies an active area of 0.07 mm2 and consumes 59.4 mW at 10 GHz. The measured results show that it achieves 56.1 fs rms-jitter and −57.13 dBc spur level. The calculated figure-of-merit (FOM) is −247.3 dB, which is better than previous RILCMs and even comparable to those large-area LC-ILCMs.

A 4–40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS

This paper presents a 4–40 Gb/s current mode PAM4 transmitter with an optimized eye linearity. By embedding an additional mixed combiner and an extra current source into the output driver and developing a coherent scaled-replica based bias generator, the channel-length modulation caused tail-current variations for both DC and AC coupling modes can be effectively compensated. Implemented in 65 nm CMOS, the transmitter occupies an area of 1.02 mm2 and consumes 102 mW at 40 Gb/s. After applying the proposed linearity optimization, the measured eye linearity can be optimized from 1.28 to 1.01 with a single-end swing of 480 mV in AC coupling mode.

A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS

This paper presents a 40-Gb/s transmitter (TX) and receiver (RX) chipset for chip-to-chip communications in a 65-nm CMOS process. The TX implements a quarter-rate multi-multiplexer (MUX)-based four-tap feed-forward equalizer (FFE), where a charge-sharing-effect elimination technique is introduced into the 4:1 MUX to optimize its jitter performance and power efficiency. The RX employs a two-stage continuous-time linear equalizer as the analog front end and integrates a low-cost sign-based zero-forcing engine relying on edge-data correlation to automatically adjust the tap weights of the TX-FFE. By embedding low-pass filters with an adaptively adjusting bandwidth into the data-sampling path and adopting high-linearity compensating phase interpolators, the clock data recovery achieves both high jitter tolerance and low jitter generation. The fabricated TX and RX chipset delivers 40-Gb/s PRBS data at BER < 10−12 over a channel with > 16-dB loss at half-baud frequency, while consuming a total power of 370 mW.

A 50Gb/s low power PAM4 SerDes transmitter with 4-tap FFE and high linearity output voltage in 65nm CMOS technology

This paper presents a 50Gb/s low power PAM4 transmitter with 4-tap FFE and high linearity output voltage. By employing a low voltage cascode current mirror under the output driver, the nonlinearity between the high and low bit output current is reduced. In addition, the output Vpp reaches 1V. Replacing the hungry CML latch by the transmission gate and realizing the data delay for pre-emphasis at former stage, the consumption of the transmitter is reduced at this high rate. Simulation result shows that, the four-level-signal has clear eye diagram when passing through a channel model with 14.3dB attenuation at 12.5GHz. The output has minimum vertical eye opening of 119mVpp and minimum horizontal eye width of 21ps (0.52UI). The active chip area of the whole transceiver is 0.61mm × 0.92mm. Performed in 65 nm CMOS technology, the transmitter running at 50Gb/s consumes 66mW power under 1.2 V supply.