Y. Helen

Nd:YVO 4 Laser Crystallization for Thin Film Transistors with a High Mobility

We crystallize amorphous silicon films with a frequency doubled Nd:YVO 4 laser operating at a repetition frequency of up to 50 kHz. A sequential lateral solidification process yields polycrystalline silicon with grains longer than 100 μm and a width between 0.27 and 1.7 μm depending on film thickness and laser repetition frequency. The average grain size is constant over the whole crystallized area of 25 cm 2 . Thin film transistors with n- type and p-type channels fabricated from the polycrystalline films have average field effect mobilities of μ n = 467 cm 2 /Vs and μ p = 217 cm 2 /Vs respectively. As a result of the homogeneous grain size distribution, the standard deviation of the mobility is only 5%.

Analysis of the activation energy of the subthreshold current in laser- and solid-phase-crystallized polycrystalline silicon thin-film transistors

Analysis of the thermal and gate-voltage dependences of the current in the subthreshold region is performed on both low-temperature laser-crystallized and solid-phase-crystallized polycrystalline silicon (polysilicon) thin-film transistors (TFTs). Temperature measurements are made at first in order to extract the variations of the activation energy EA of the drain current with the gate voltage. The plot of the subthreshold current versus the measured activation energy leads to an apparent activation energy EA/n, where the n factor is extracted from the slope of this plot. The n factor is close to 1 for laser-crystallized polysilicon TFTs while it is rather close to 2 for solid-phase-crystallized ones. These two values can be attributed to a different defect distribution in the two differently crystallized TFTs polysilicon active layers.

High mobility thin film transistors by Nd:YVO4-laser crystallization

Abstract Laser crystallization of amorphous silicon is one of the most interesting ways to obtain high-quality polycrystalline silicon films on glass. We crystallized the channel region of n- and p-type thin film transistors (TFTs) with a frequency-doubled Nd:YVO 4 laser utilizing a sequential lateral solidification process. The high repetition rate of the laser of up to 100 kHz allows for high scanning speeds of up to 5 cm s −1 . The laser irradiation was performed in air at room temperature. The resulting polycrystalline films showed longitudinally elongated grains with a length of up to 100 μm in the scanning direction of the laser beam and a width of up to 2 μm perpendicular to the scanning direction. Due to the anisotropic grain dimensions, the TFT performance depends on the orientation of the channel with respect to the scanning direction. Furthermore, a scale down of the TFT dimensions results in a better device performance because the number of grain boundaries within the channel of a TFT is reduced. For example, a decrease in the width W and length L of the channel from W =63 and L =22 μm to W =30 and L =15 μm increases the field-effect electron mobility μ N of the TFTs from μ N =410 to 510 cm 2 V −1 s −1 . The high mobility μ and low sub-threshold slope S =0.45 V decade −1 obtained with a gate oxide thickness of 100 nm show the high quality of laser-crystallized polycrystalline silicon.

Comparison of the electrical behavior in the subthreshold region between laser and solid phase crystallized polysilicon thin film transistors

Abstract Electrical properties in the subthreshold region are studied in two types of field effect transistors: laser crystallized-polysilicon thin film transistors (LC-TFTs) and solid phase crystallized-polysilicon thin film transistors (SPC-TFTs). For LC-TFT the active layer is crystallized by using one shot of a very large area excimer laser with a fluence of 600 mJ/cm2, whereas the active layer for SPC-TFT is crystallized by a thermal annealing at 600 °C in vacuum. LC polysilicon layer exhibits a higher degree of crystallinity than the SPC one. Electrical measurements on the TFTs are performed from room temperature to 120 °C. The analysis of the transfer characteristics shows that the subthreshold current is thermally activated with a different gate voltage dependence for each type of TFTs. The electrical behavior in the subthreshold region is correlated with the quality of the polysilicon active layer. For LC-TFT, conduction is mainly due to thermal emission of carriers over intergranular barrier energy, and it is convenient with a discrete distribution of defects in the active layer, mainly located at the grain boundaries. On the other hand, for SPC-TFTs, a mechanism of multiple-trapping and/or generation/recombination process of carriers from defects, rather uniformly distributed in the active layer, predominates in the electrical conduction.

Ageing of laser crystallized and unhydrogenated polysilicon thin film transistors

Abstract Ageing of low temperature polysilicon Thin Film Transistors (TFTs) is reported in this study. The active layer of these high performances transistors is amorphous deposited using Low Pressure Chemical Vapor Deposition (LPCVD) technique and then laser crystallized using a single shot ECL (SSECL of SOPRA) with very large excimer laser. The drain and source regions are in-situ doped during the LPCVD deposition by using phosphine or diborane to fabricate n-type or p-type transistors respectively. These laser crystallized TFTs show poorer reliability properties than solid-phase crystallized TFTs. This poor stability is explained to originate from the high surface roughness produced by the laser crystallization, which is highlighted from Atomic Force Microscopy observations. Moreover to this conclusion, the behaviour of the threshold voltage shift ΔV T during positive and negative stresses is checked to the light of a stretched exponential law that is, as supposed, a federative law. This law is explained in hydrogenated amorphous silicon TFTs by a dispersive diffusion coefficient of hydrogen in the disordered material. Taking into account that such relation appears as sufficiently general and, particularly, can describe the behaviour of monocrystalline silicon MOSFET and un-hydrogenated polysilicon TFTs where the hydrogen cannot involved, it can be supposed that it deals with disordered materials and disordered regions in crystalline materials (interface, grain boundary, …..).

Stability of unhydrogenated polysilicon thin film transistors and structural quality of the channel material

Abstract The performance of polysilicon thin film transistors used in large-area electronics applications, directly depends on the structural quality of the channel material. Moreover, their stability under electrical stress is shown, in this work, to also depend on the quality of the channel material. TFTs were fabricated using several channel materials, deposited as an amorphous film by low-pressure chemical vapor deposition (LPCVD), and then crystallized using solid-phase annealing, a large-area pulsed excimer laser, or scanning with a 532-nm beam of a pulsed diode pumped Nd:YVO4 laser. The stability of the TFTs, determined from the increase in the subthreshold slope S, is shown to be related to the importance of the surface roughness and to the structural quality of the crystallized active layer. With similar surface roughness, the stability is better when the structural quality of the active layer is improved. The increase in S is then explained by the creation of a state in the channel material that is more effective when the structure of the polysilicon is more disordered.

Stability of polysilicon thin film transistors under switch operating

Abstract Ageing of low temperature polysilicon Thin Film Transistors (TFTs) under AC gate bias stress is reported in this study. The active layer of these high performances transistors is amorphous deposited using Low Pressure Chemical Vapor Deposition (LPCVD) technique. The drain and source regions are in-situ doped during the LPCVD deposition by using phosphine to fabricate n-type transistors. The active layer and the drain arid source regions are Solid Phase Crystallized. The field effect mobility is higher than 100 cm2/V.s, the subthreshold slope around 0.6 V/dec, the threshold voltage around 0.2V and the switching time around 370 nsec. As these TFTs are commonly used as switching devices in the most of applications in large area electronics field, the study of their stability under AC electrical stress is important. The present work shows that the effect of the positive or negative DC stress is higher than that of the AC stress and then the degradation of polysilicon TFTs is over-estimated when it is checked from the effects of DC gate bias stress. Degradation under bias stress is shown to originate from the creation of gap states at the channel-interface oxide and in the channel material. The lower influence of the AC stress is explained from an annealing effect of the created states by the application of an opposite sign bias stress.