Y. Ikemoto

First Performance Evaluation of an X-Ray SOI Pixel Sensor for Imaging Spectroscopy and Intra-Pixel Trigger

We have been developing a monolithic active pixel sensor with the 0.2 μm Silicon-On-Insulator (SOI) CMOS technology, called SOIPIX, for the wide-band X-ray imaging spectroscopy on future astronomical satellites. SOIPIX includes a thin CMOS-readout-array layer and a thick high-resistivity Si-sensor layer stacked vertically on a single chip. This arrangement allows for fast and intelligent readout circuitries on-chip, providing advantages over the charge-coupled device (CCD). We have designed and built a new SOIPIX prototype XRPIX1 for X-ray detection. XRPIX1 implements a correlated double sampling (CDS) readout circuit in each pixel to suppress the reset noise. We obtained an energy resolution of full width at half maximum of 1.2 keV (5.4%) at 22 keV with a chip having a 147 μm sensor depletion at a back bias of 100 V cooled to -50°C. Moreover, XRPIX1 offers intra-pixel hit trigger (timing) and two-dimensional hit-pattern (position) outputs. We also confirmed the trigger capability by irradiating a single pixel with laser light.

Radiation Resistance of SOI Pixel Devices Fabricated With OKI 0.15

Silicon-on-insulator (SOI) technology is being investigated for monolithic pixel device fabrication. The SOI wafers by UNIBOND allow the silicon resistivity to be optimized separately for the electronics and detector parts. We have fabricated pixel detectors using fully depleted SOI (FD-SOI) technology provided by OKI Semiconductor Co. Ltd. The first pixel devices consisting of 32×32 pixels each with 20 μm square were irradiated with ⁶⁰Co γ’s up to 0.60 MGy and with 70-MeV protons up to 1.3×10¹⁶ 1-MeV n<inf>eq</inf>/cm². The performance characterization was made on the electronics part and as a general detector from the response to RESET signals and to laser. The electronics operation was affected by radiation-induced charge accumulation in the oxide layers. Detailed evaluation using transistor test structures was separately carried out with covering a wider range of radiation level (0.12 kGy to 5.1 MGy) with ⁶⁰Co γ’s.Silicon-on-insulator (SOI) technology is being investigated for monolithic pixel device fabrication. The SOI wafers by UNIBOND allow the silicon resistivity to be optimized separately for the electronics and detector parts. We have fabricated pixel detectors using fully depleted SOI (FD-SOI) technology provided by OKI Semiconductor Co. Ltd. The first pixel devices consisting of 32times32 matrix with 20 mum times 20 mum pixels were irradiated with 60Co gammas up to 0.60 MGy and with 70-MeV protons up to 9.3times10 60Co p/cm2. The performance characterization was made on the electronics part and as a photon detector from the response to reset signals and to laser. The electronics operation was affected by radiation-induced charge accumulation in the oxide layers. Detailed evaluation of the characteristics changes in the transistors was separately carried out using transistor test structures to which a wider range of irradiation, from 0.12 kGy to 5.1 MGy, was made with 60Co gammas.

\mu {\rm m}

Monolithic pixel devices fabricated with a siliconon-Insulator (SOI) technology are excellent candidates to realize particle detectors of fast response and least material yet simple in fabrication. In our SOI pixel devices the sensitive part is the “handle” wafer, to which we examined high resistive FZ wafers of both p- and n-types together with CZ wafer of n-type. Full depletion of the FZ wafers is easily achievable for typical thicknesses of 260 to 500 µm. We thinned these devices to 100 to 50 µm. The response was evaluated with infrared and red lasers, and in a high energy beam. Irradiation to 60Co γ was carried out to verify the radiation tolerance of the devices.

FD-SOI Technology

We are developing monolithic pixel devices utilizing a 0.2 μm Fully Depleted Silicon-on-Insulator (FD-SOI) process technology provided by OKI Semiconductor. We have investigated thinning the devices to 100 μm. Thinning enhances the feature of monolithic SOI sensors in views of minimizing the overall material and realizing full depleted devices. The latter is necessary for backside illumination, which is desirable to enhance the photo sensitivity. The wafer was thinned commercially by DISCO Corp. Small increase in the leakage current was observed associated with the thinning process. Excellent performance to infrared and red laser lights was obtained, demonstrating realization of the fully depleted pixel device.

Development of FD-SOI monolithic pixel devices for high-energy charged particle detection

The high-luminosity Large Hadron Collider (HL-LHC) upgrade project aims to increase the LHC peak luminosity up to 5×1034 cm-2s-1 and the integrated luminosity up to3000 fb-1. To achieve this goal, the quadrupole and dipole magnets around the two interaction points, i.e., the ATLAS and the CMS, will be upgraded. The High Energy Accelerator Research Organization (KEK) is in charge of the development of beam separation dipole (D1). In new D1, the coil aperture is enlarged to be 150 mm, and an integrated field of 35 T · m is required at 1.9 K and 12.0 kA. This paper reports the current status of the development of a 2-m model magnet.

Evaluation of monolithic Silicon-on-Insulator pixel devices thinned to 100 μm

The High Energy Accelerator Research Organization (KEK) has been developing a Nb3Al and Nb3Sn subscale magnet to establish the technology for a high-field accelerator magnet. The development goals are a feasibility demonstration for a Nb3Al cable and the technology acquisition of magnet fabrication with Nb3Al superconductors. KEK developed two double-pancake racetrack coils with Rutherford-type cables composed of 28 Nb3Al wires processed by rapid heating, quenching, and transformation in collaboration with the National Institute for Materials Science and the Fermi National Accelerator Laboratory. The magnet was fabricated to efficiently generate a high magnetic field in a minimum-gap common-coil configuration with two Nb3Al coils sandwiched between two Nb3Sn coils produced by the Lawrence Berkeley National Laboratory. A shell-based structure and a “bladder and key” technique have been used for adjusting coil prestress during both the magnet assembly and the cool down. In the first excitation test of the magnet at 4.5 K performed in June 2014, the highest quench current of the Nb3Sn coil, i.e., 9667 A, was reached at 40 A/s corresponding to 9.0 T in the Nb3Sn coil and 8.2 T in the Nb3Al coil. The quench characteristics of the magnet were studied.

Development Status of a 2-m Model Magnet of Beam Separation Dipole for the HL-LHC Upgrade

We are developing monolithic pixel detector using fully-depleted (FD) silicon-on-insulator (SOI) pixel process technology. The SOI substrate is high resistivity silicon with p-n junctions and another layer is a low resistivity silicon for SOI-CMOS circuitry. Tungsten vias are used for the connection between two silicons. Since flip-chip bump bonding process is not used, high sensor gain in a small pixel area can be obtained. In 2010 and 2011, high-resolution integration-type SOI pixel sensors, DIPIX and INTPIX5, have been developed. The characterizations by evaluating pixel-to-pixel crosstalk, quantum efficiency (QE), dark noise, and energy resolution were done. A phase-contrast imaging was demonstrated using the INTPIX5 pixel sensor for an X-ray application. The current issues and future prospect are also discussed.

Test results of a Nb3Al/Nb3Sn subscale magnet for accelerator application

We are developing monolithic pixel detectors with a 0.2 µm CMOS, fully-depleted silicon-on-insulator (SOI) technology. The substrate is high-resistivity silicon and works as a radiation sensor having p-n junctions. The SOI layer is a 40 nm thick silicon, where readout electronics is implemented. There is a buried oxide (BOX) layer between these silicon layers. We have already done several Multi Project Wafer (MPW) runs by gathering many pixel designs into a photo mask set, and as the results, several types of integration type pixel detectors (INTPIX) were fabricated. In this document, the design concept and performance in some of INTPIX detectors are described.

SOI monolithic pixel detector

We have been developing a monolithic active pixel sensor with the 0.2 μm Silicon-On-Insulator (SOI) CMOS technology, i.e. SOIPIX, for the X-ray imaging spectroscopy on future astronomical satellites. SOIPIX includes a thin CMOS readout layer and a thick high-resistivity Si-sensor layer vertically on a single chip, which would provide advantages in capabilities of direct and flexible readout circuitries over charge-coupled device (CCD). We have built INTPIX2/3 (2008/2009) and XRPIX1(2010). We successfully confirmed the capability of X-ray imaging and spectroscopy in a photon-counting mode by irradiating INTPIX2/3 with monochromatic X-rays. To reduce the readout noise, we designed and built XRPIX1, which has a correlated double sampling (CDS) readout circuit in each pixel to suppress the reset noise. We obtained an energy resolution of FWHM ∼1.5 keV(7%)@22 keV with XRPIX1 cooled at 50 degree. Moreover, XRPIX1 offers intra-pixel hit trigger and one-dimensional hit-pattern outputs. We also confirmed the trigger capability by irradiating a single pixel of XRPIX1 with laser light.

Performance study of monolithic pixel detectors fabricated with FD-SOI technology

Silicon-on-insulator (SOI) technology is being investigated for monolithic pixel device fabrication. The SOI wafers by UNIBOND allow the silicon resistivity to be optimized separately for the electronics and detector parts. We have fabricated pixel detectors using fully depleted SOI (FD-SOI) technology provided by OKI Semiconductor Co. Ltd. The first pixel devices consisting of 32×32 pixels each with 20 μm square were irradiated with 60Co γ’s up to 0.60 MGy and with 70-MeV protons up to 1.3×1016 1-MeV n eq /cm2. The performance characterization was made on the electronics part and as a general detector from the response to RESET signals and to laser. The electronics operation was affected by radiation-induced charge accumulation in the oxide layers. Detailed evaluation using transistor test structures was separately carried out with covering a wider range of radiation level (0.12 kGy to 5.1 MGy) with 60Co γ’s.