Y.Q. Wu

High-Performance Inversion-Type Enhancement-Mode InGaAs MOSFET With Maximum Drain Current Exceeding 1 A/mm

High-performance inversion-type enhancement- mode (E-mode) n-channel In_0.65Ga_0.35As MOSFETs with atomic-layer-deposited Al₂O₃ as gate dielectric are demonstrated. A 0.4-mum gate-length MOSFET with an Al₂O₃ gate oxide thickness of 10 nm shows a gate leakage current that is less than 5 times 10^-6 A/cm² at 4.0-V gate bias, a threshold voltage of 0.4 V, a maximum drain current of 1.05 A/mm, and a transconductance of 350 mS/mm at drain voltage of 2.0 V. The maximum drain current and transconductance scale linearly from 40 mum to 0.7 mum. The peak effective mobility is ~1550 cm²/V ldr s at 0.3 MV/cm and decreases to ~650 cm²/V ldr s at 0.9 MV/cm. The obtained maximum drain current and transconductance are all record-high values in 40 years of E-mode III-V MOSFET research.

Top-gated graphene field-effect-transistors formed by decomposition of SiC

Top-gated, few-layer graphene field-effect transistors (FETs) fabricated on thermally decomposed semi-insulating 4H-SiC substrates are demonstrated. Physical vapor deposited SiO2 is used as the gate dielectric. A two-dimensional hexagonal arrangement of carbon atoms with the correct lattice vectors, observed by high-resolution scanning tunneling microscopy, confirms the formation of multiple graphene layers on top of the SiC substrates. The observation of n-type and p-type transition further verifies Dirac Fermions’ unique transport properties in graphene layers. The measured electron and hole mobilities on these fabricated graphene FETs are as high as 5400 and 4400cm2∕Vs, respectively, which are much larger than the corresponding values from conventional SiC or silicon.

Atomic-layer-deposited nanostructures for graphene-based nanoelectronics

Graphene is a hexagonally bonded sheet of carbon atoms that exhibits superior transport properties with a velocity of 108cm∕s and a room-temperature mobility of >15000cm2∕Vs. How to grow gate dielectrics on graphene with low defect states is a challenge for graphene-based nanoelectronics. Here, we present the growth behavior of Al2O3 and HfO2 films on highly ordered pyrolytic graphite (HOPG) by atomic layer deposition (ALD). To our surprise, large numbers of Al2O3 and HfO2 nanoribbons, with dimensions of 5–200nm in width and >50μm in length, are observed on HOPG surfaces at growth temperature between 200 and 250°C. This is due to the large numbers of step edges of graphene on HOPG surfaces, which serve as nucleation sites for the ALD process. These Al2O3 and HfO2 nanoribbons can be used as hard masks to generate graphene nanoribbons or as top-gate dielectrics for graphene devices. This methodology could be extended to synthesize insulating, semiconducting, and metallic nanostructures and their combinations.

Submicrometer Inversion-Type Enhancement-Mode InGaAs MOSFET With Atomic-Layer-Deposited

High-performance inversion-type enhancement-mode n-channel In_0.53Ga_0.47As MOSFETs with atomic-layer-deposited (ALD) Al₂O₃ as gate dielectric are demonstrated. The ALD process on III-V compound semiconductors enables the formation of high-quality gate oxides and unpinning of Fermi level on compound semiconductors in general. A 0.5-mum gate-length MOSFET with an Al₂O₃ gate oxide thickness of 8 nm shows a gate leakage current less than 10^-4 A/cm² at 3-V gate bias, a threshold voltage of 0.25 V, a maximum drain current of 367 mA/mm, and a transconductance of 130 mS/mm at drain voltage of 2 V. The midgap interface trap density of regrown Al₂O₃ on In_0.53Ga_0.47As is ~1.4 x 10¹²/cm² ldr eV which is determined by low-and high-frequency capacitance-voltage method. The peak effective mobility is ~1100 cm² / V ldr s from dc measurement, ~2200 cm²/ V ldr s after interface trap correction, and with about a factor of two to three higher than Si universal mobility in the range of 0.5-1.0-MV/cm effective electric field.

\hbox{Al}_{2}\hbox{O}_{3}

Epitaxial graphene films examined were formed on the Si-face of semi-insulating 4H-SiC substrates by a high temperature sublimation process. A high-k gate stack on the epitaxial graphene was realized by inserting a fully oxidized nanometer thin aluminum film as a seeding layer, followed by an atomic-layer deposition process. The electrical properties of epitaxial graphene films are retained after gate stack formation without significant degradation. At low temperatures, the quantum-Hall effect in Hall resistance is observed along with pronounced Shubnikov–de Haas oscillations in diagonal magnetoresistance of gated epitaxial graphene on SiC (0001).

as Gate Dielectric

The first well-behaved inversion-mode InGaAs FinFET with gate length down to 100 nm with ALD Al2O3 as gate dielectric has been demonstrated. Using a damage-free sidewall etching method, FinFETs with Lch down to 100 nm and WFin down to 40 nm are fabricated and characterized. In contrast to the severe short-channel effect (SCE) of the planar InGaAs MOSFETs at similar gate lengths, FinFETs have much better electro-static control and show improved S.S., DIBL and VT roll-off and less degradation at elevated temperatures. The SCE of III-V MOSFETs is greatly improved by the 3D structure design. The more accurate Dit estimation from the S.S. is also presented.

Observation of quantum-Hall effect in gated epitaxial graphene grown on SiC (0001)

Epitaxial graphene films have been formed on the C-face of semi-insulating 4H-SiC substrates by a high temperature sublimation process. Nanoscale square antidot arrays have been fabricated on these graphene films. At low temperatures, magnetoconductance in these films exhibits pronounced Aharonov–Bohm oscillations with the period corresponding to magnetic flux quanta added to the area of a single antidot. At low fields, weak localization is observed and its visibility is enhanced by intervalley scattering on antidot edges. At high fields, we observe two distinctive minima in magnetoconductance, which can be attributed to commensurability oscillations between classical cyclotron orbits and antidot array. All mesoscopic features, surviving up to 70K, reveal the unique electronic properties of graphene.

First experimental demonstration of 100 nm inversion-mode InGaAs FinFET through damage-free sidewall etching

We have systematically studied NMOSFETs, MOSCAPs, and the interfacial chemistry on GaAs (100), (110), (111)A and (111)B-four different crystalline surfaces with direct ALD Al2O3. We found that a much higher drain current on GaAs(111)A NMOSFET can be achieved compared to that obtained on the other 3 surfaces. Also, the results of MOS-CAPs and the interfacial chemistry obtained on the (111)A surface are very different from those others. These experimental results conclusively demonstrate that Fermi-level on the GaAs (111)A surface is indeed unpinned and Fermi-level pinning is not an intrinsic property of GaAs, but is orientation dependent thus related to surface chemistry.

Magnetoconductance oscillations in graphene antidot arrays

We performed gate ramp voltage stress on III-V InGaAs based MOSFETs. Stress induces trapped charge and it also leads to interface trap generation, which has detrimental effects on the subthreshold slope and on the transconductance. At high electric fields, before the hard breakdown, a very low-frequency high-current random telegraph noise appears at the gate, which seems to be not correlated with the soft breakdowns commonly observed in other devices.

New insight into Fermi-level unpinning on GaAs: Impact of different surface orientations

In this paper, we report, for the first time, the observation of n-type and p-type transition on epitaxially grown graphene films by top-gate bias. More importantly, the measured electron and hole mobility on fabricated top-gate graphene field-effect transistors exceeds 1500 cm2/Vs and 3400 cm2/Vs, respectively.