Y. Tamaki

Creep curve of silicon wafers

A new method of performing a creep test on silicon single crystals is described. The experiment utilizes silicon wafers. The stress applied to the wafers is provided by a Si3N4 film deposited by chemical vapor deposition on the front side of the wafer. The samples, i.e., silicon wafers with superposed Si3N4 films, are annealed in a quartz tube at 1000–1100 °C. The creep curves obtained are classified into two types according to stress. One type is related to plastic deformation of the wafer; the other is an elastic deformation. These results are available for the use of Si3N4 film in semiconductor technology.

Evaluation of Dislocation Generation at Si3 N 4 Film Edges on Silicon Substrates by Selective Oxidation

The density of dislocations generated at film edges on silicon substrate by selective oxidation is measured and the relation between the selective oxidation conditions and dislocation generation at the film edges is investigated. Dislocations are observed using Secco etching. The results show that the density of dislocations does not continuously increase with oxidation temperature, but decreases markedly at temperatures above 1000°C. A further experiment with recessed oxide structure reveals that the generation of dislocations depends strongly on the cross‐sectional structure of the sample These results are interpreted in terms of viscous flow of film. Another experiment suggests that high pressure oxidation is not effective for suppressing dislocation generation, although it is useful for reducing oxidation time. Finally, collector‐emitter shorts of transistors in bipolar integrated circuits are examined quantitatively using a simple statistical method in relation to the dislocations generated at film edges.

Ultrashallow p‐type layer formation by rapid vapor‐phase doping using a lamp annealing apparatus

Ultrashallow p‐type layers below 30 nm were formed by a rapid vapor‐phase doping involving a lamp annealing system. A new one‐wafer‐type apparatus with tungsten lamps has been developed for use in this process. Temperatures at five different points on a 4‐in. wafer are in situ monitored by infrared radiative thermometers with optical fibers to maintain a uniform temperature profile across the wafer. By using hydrogen and B2H6 gas, an ultrashallow boron‐doped layer of below 30 nm with the surface boron concentration of 5.8×1019 cm−3 was formed after 10 s of 900 °C annealing with a B2H6 flow rate of 100 ml/min.

A very small bipolar transistor technology with sidewall polycide base electrode for ECL-CMOS LSIs

Very small, high-performance, silicon bipolar transistors (SPOTEC) are developed for use in ECL-CMOS LSIs. The transistors are fabricated with a sidewall polycide base; chemical vapor deposition is used to selectively deposit tungsten on the sidewall surface of the polysilicon base. The tungsten is then silicided. This self-aligned polycide technology makes a narrow (0.4-/spl mu/m wide), low-resistance (7 /spl Omega///spl square/) base electrode possible. Narrow U-groove isolation and narrow collector metallization techniques are used to reduce the transistor area to 10 /spl mu/m/sup 2/. A shallow E-B junction and base layer have now been formed by using rapid-vapor-phase doping. The resulting transistors have good I-V characteristics without leakage current or high current gain. They have a high cut-off frequency of 37 GHz (53 GHz with pedestal collector ion implantation and thin epitaxial layer) and small junction capacitances. These transistors facilitate the development of very-high-speed, high-density ULSIs.

Double‐Layer μc ‐ Si / a ‐ SiC x Emitter in a Silicon Heterojunction Bipolar Transistor with a Cutoff Frequency of 47 GHz

We have fabricated a heteroemitter that consists of a microcrystalline silicon (μc-Si) and a very thin carbon-doped amorphous crystalline silicon (a-SiC x ) double layer which is optimized for high emitter efficiency and high-speed transistor action. The emitter layer was deposited using electron cyclotron resonance, plasma-enhanced chemical vapor deposition. Critical factors for the optimization are treatments of the substrate surface before deposition of the emitter layer and the temperature and SiH 4 /CH 4 gas ratio during deposition of the very thin a-SiC x layer. The emitter efficiency of transistors using the heteroemitter is two to three times higher than that of conventional polysilicon emitter bipolar transistors, and the emitter resistance of the transistors is reduced to only three times that of conventional transistors. A self-aligned silicon heterojunction bipolar transistor (SiHBT) using the heteroemitter demonstrated a cutoff frequency, f T , of 47 GHz, which is almost two times larger than the highest value previously reported for SiHBTs using hydrogenated μc-Si or μc-SiC x as an emitter.

Soft-error-immune switched-load-resistor memory cell

Various memory cell sizes that can be obtained with anticipated device size reduction are compared in Fig. 9. It is clear that a future ultra-high-speed high density bipolar RAM with sufficient soft-error immunity is possible using the new memory cell.