Hisayuki Higuchi

Retardation of Sb Diffusion in Si during Thermal Oxidation

Investigation of Sb diffusion in Si during thermal oxidation using LOCOS (LOCal Oxidation of Silicon) shows that diffusion of Sb in Si is retarded during thermal oxidation. This suggests that the diffusion mechanism of Sb differs from those of B and P, which diffuse faster during thermal oxidation. A model which can explain both enhanced and retarded diffusion of impurities in Si during oxidation is proposed. The model assumes that B and P diffuse only by interstitials, Sb diffuses only by vacancies and As diffuses by both vacancies and interstitials.

Effect of Si and SiO2 thermal nitridation on impurity diffusion and oxidation induced stacking fault size in Si

The effect of thermal nitridation on impurity diffusion and Oxidation induced Stacking Fault size in Si are clarified by selective nitridation. Enhanced B and P diffusion, retarded Sb diffusion, and growth of OSF’s are found in Si masked with SiO2 films. Retarded B and P diffusion, enhanced Sb diffusion and rapid OSF shrinkage are found in nonmasked Si that has undergone NH3 heat treatment. On the other hand, in N2 or N2+H2 (1:3) ambients, no significant ambient effect on impurity diffusion is found in Si masked with SiO2 films. However, retarded B and P diffusion and enhanced Sb diffusion are found in nonmasked Si with N2 ambient. The results are shown to be consistent with the model that shows that interstitials and vacancies effect thermal equilibrium.

Advanced BiCMOS technology for high speed VLSI

This paper describes the high performance BiCMOS (Hi-BiCMOS) device technology and discusses the scalability to sub-micron. As the device structure is scaled down from 2 µm to 1.3 µm, BiCMOS circuit performance is improved by the factor of the scaling. By further scale down to 0.8 µm, a 0.27 ns gate delay in BiCMOS gate and 5.5 ns access time of 64kbit BiCNOS ECL RAN are expected.

A 2 ns access, 285 MHz, two-port cache macro using double global bit-line pairs

High bandwidth has become one of the most important features in high-speed embedded cache memories in recent superscalar RISC processors. This 285 MHz, two-port 16kB (512/spl times/256) cache macro has a 2 ns access time. In this cache, the data of memory cells are sent to a read bus in the first half of the cycle time, and write data from a write bus are written to memory cells in the second half of the cycle time. This performance is achieved because of a hierarchical bit-line architecture that uses double global bit-line pairs (WGB), and a high-speed timing-free sense amplifier that shortens access time.

Anomalous Diffusion of B and P in Si Directly Masked with Si3N4

Diffusion of B and P in Si directly masked with Si3N4 films is found to have anomalous characteristics depending on temperature, time, and Si crystal growing method. The discrepancy in diffusion between CZ and FZ substrates under Si3N4 films is explained well assuming the Si–SiO2 interface acts as a sink for super-saturated interstitials. The Si–Si3N4 interface does not have such an effect. It is also found that super-saturated interstitials enhance the diffusion of B and P in CZ Si crystals directly masked with Si3N4 films.

A 3.5-ns, 500-mW, 16-kbit BiCMOS ECL RAM

A 16-Kb RAM was designed and fabricated using a 0.5- mu m BiCMOS technology. It has a typical address access time of 3.5 ns. The RAM operates at a supply voltage of -4.5 V and features 500-mW power dissipation. A description is given of two techniques crucial to high-speed, low-power design: a wired -OR precoder combined with a low-power, high-speed level converter circuit and a direct column-sensing circuit with a cascode differential amplifier.<<ETX>>

Performance and structures of scaled-down bipolar devices merged with CMOSFETs

Fabricating BiCMOS test samples, performance and structures of 2 µm and scaled BiCMOS are evaluated. The developed BiCMOS processes realize almost the same device characteristics of bipolar and CMOS LSIs fabricated with the same lithographic technology. The intrinsic delays of BiCMOS and CMOS 2-NAND circuits are 0.5 ns and 0.4 ns respectively. The delay times are comparable with the bipolar ECL circuits. The BiCMOS technology makes it possible to fabricate high-speed, low-power dissipation, high-packing density LSIs by sharing the roles among them.

Effects of Oxidation on Aluminum Diffusion in Silicon

Aluminum diffusion in Si affected by thermal oxidation is investigated. Aluminum diffusion in (100) oriented Si is enhanced by thermal oxidation. On the other hand, that in (111) oriented Si is enhanced at low temperature but retarded at high temperature. The difference in the diffusion of Al in Si masked with double-layered SiO2–Si3N4 films and with directly-formed Si3N4 films is found to be very small compared to the case of B and P. Furthermore, the addition of HCl to the oxidizing ambient is found to reduce the anomalous diffusion caused by oxidation. These experimental results are explained assuming that the diffusion of Al in Si proceeds by the interstitialcy mechanism in the Si.

Evaluation of Dislocation Generation at Si3 N 4 Film Edges on Silicon Substrates by Selective Oxidation

The density of dislocations generated at film edges on silicon substrate by selective oxidation is measured and the relation between the selective oxidation conditions and dislocation generation at the film edges is investigated. Dislocations are observed using Secco etching. The results show that the density of dislocations does not continuously increase with oxidation temperature, but decreases markedly at temperatures above 1000°C. A further experiment with recessed oxide structure reveals that the generation of dislocations depends strongly on the cross‐sectional structure of the sample These results are interpreted in terms of viscous flow of film. Another experiment suggests that high pressure oxidation is not effective for suppressing dislocation generation, although it is useful for reducing oxidation time. Finally, collector‐emitter shorts of transistors in bipolar integrated circuits are examined quantitatively using a simple statistical method in relation to the dislocations generated at film edges.

A 7ns/350mW 64K ECL compatible RAM

A 64K×1 ECL RAM using 1.3μm bipolar-CMOS technology including bipolar transistor with a 7GHz cutoff frequency will be presented. Variable impedance and equalizing circuitry permit 7ns access time. Power dissipation is 350mW.