Kazuhiko Sagara

A 0.72 mu m/sup 2/ recessed STC (RSTC) technology for 256 Mbit DRAMs using quarter-micron phase-shift lithography

A recessed stacked capacitor (RSTC) structure to achieve both fine-pattern delineation and high cell capacitance is presented. Using a RSTC structure, an experimental memory array with 0.25 mu m phase-shift lithography and CVD-W plate technology has been fabricated. A 25-fF/cell capacitance was obtained in a 0.72 mu m/sup 2/ cell.<<ETX>>

256-Mb DRAM circuit technologies for file applications

256-Mb DRAM circuit technologies characterized by low power and high fabrication yield for file applications are described. The newly proposed and developed circuits are a self-reverse-biasing circuit for word drivers and decoders to suppress the subthreshold current to 3% of the conventional scheme, and a subarray-replacement redundancy technique that doubles chip yield and consequently reduces manufacturing costs. An experimental 256-Mb DRAM has been designed and fabricated by combining the proposed circuit techniques and a 0.25- mu m phase-shift optical lithography, and its basic operations are verified. A 0.72- mu m/sup 2/ double-cylindrical recessed stacked-capacitor (RSTC) cell is used to ensure a storage capacitance of 25 fF/cell. A typical access time under a 2-V power supply voltage was 70 ns. With the proper device characteristics, the simulated performances of the 256-Mb DRAM operating with a 1.5-V power supply voltage are a data-retention current of 53 mu A and an access time of 48 ns. >

256 Mb DRAM technologies for file applications

The authors describe 256-Mb DRAM (dynamic random access memory) technologies for file applications. A subthreshold-current limiting scheme for word drivers is shown. The scheme uses a pMOS switching transistor between the wordline voltage and the driver transistor common-source terminal. The subthreshold current of a 256-Mb DRAM is reduced to 3% by applying this scheme to word drivers and decoders, and the total data-retention current is less than that of a 64-Mb DRAM. A redundancy technique is shown which features subarray-by-subarray replacement instead of the conventional line-by-line replacement. To evaluate the circuit technologies described here, an experimental 256-Mb DRAM was fabricated using 0.25- mu m CMOS technology with phase-shift lithography. It uses a 0.72- mu m/sup 2/ RSTC cell with a storage capacitance of 25 fF and operates on a voltage of 1.5-3.6 V.<<ETX>>

Effect of grain size on conduction mechanism in polycrystalline silicon

Amorphous silicon was deposited on SiO2 in ultrahigh vacuum and annealed for 8 h at 600 °C in a nitrogen atmosphere. Transmission electron microscopy shows a columnar structure of polycrystalline silicon with the average grain size of 2.5 μm. Boron doses of 3×1013–6×1014 cm−2 were implanted at 30 keV into those films and annealed for 20 min at 950 °C. Hall and resistivity measurements show that the carrier concentration was 100% of the doping concentration and the hole mobility was 20–60 cm2/V s. It was also found that the dependence of hole mobility on carrier concentration is in good agreement with that for the fine grain polycrystalline silicon.

A circuit technology for sub-10-ns ECL 4-Mb BiCMOS DRAM's

The feasibility of realizing an emitter-coupled-logic (ECL) interface 4-Mb dynamic RAM (DRAM) with an access time under 10 ns using 0.3- mu m technology is explored, and a deep submicrometer BiCMOS VLSI using this technology is proposed. Five aspects of such a DRAM are covered. They are the internal power supply voltage scheme using on-chip voltage limiters, an ECL DRAM address buffer with a reset function and level converter, a current source for address buffers compensated for device parameter fluctuation, an overdrive rewrite amplifier for realizing a fast cycle time, and double-stage current sensing for the main amplifier and output buffer. Using these circuit techniques, an access time of 7.8 ns is expected with a supply current of 198 mA at a 16-ns cycle time. >

Portable single-channel NIRS-based BMI system for motor disabilities' communication tools

A portable near-infrared spectroscopy (NIRS) -based brain-machine Interface (BMI) system featuring single-channel probe, BMI controller and Infrared-emission apparatus was developed. As a switching technology for external devices, the threshold logic was proposed, which detects the blood volume change in the operators frontal lobe. Experiments showed that the operator was able to change the TV programs or get forward the toy robot within 16 s (the mean is 11.77 s and the standard deviation is 2.35 s) after the mental calculation. In addition, the menu selection program was proposed for motor disabilities and the preliminary test showed that he could successively select the sentence from several candidates. It was shown that this system would provide the external devices control capabilities for motor disabilities.

The effect of thin interfacial oxides on the electrical characteristics of silicon bipolar devices

The effect of thin interfacial oxides on the impurity diffusion from polysilicon to the silicon substrate has been studied in detail. Polysilicon films were deposited on the silicon substrate in two different process conditions to control the thickness of interfacial oxides. Results show that the presence of about 1-nm-thick oxides retarded the impurity diffusion by about 10 nm and an increase of the sheet resistance of about 10 percent has been observed. Bipolar devices, which are sensitive to the impurity profiles, were fabricated with identical processing apart from the polysilicon deposition conditions. A detailed analysis of their electrical characteristics shows the difference of collector current components and hence the increase of current gain by about two times. These results indicate that the effect of interfacial oxides on the impurity profile is expressed by the segregation coefficientm, which is the ratio of Csi/CpolySiat the interface. The sensitivity ofmfor the device characteristics was calculated by a process-device simulator, and it is demonstrated that the current gain is a strong function ofmfor shallow emitters.

GO-STOP Control Using Optical Brain-Computer Interface during Calculation Task

We have developed a prototype optical brain-computer interface (BCI) system that can be used by an operator to manipulate external, electrically controlled equipment. Our optical BCI uses near-infrared spectroscopy and functions as a compact, practical, unrestrictive, non-invasive brain-switch. The optical BCI system measured spatiotemporal changes in the hemoglobin concentrations in the blood flow of a subjects prefrontal cortex at 22 measurement points. An exponential moving average (EMA) filter was applied to the data, and then their weighted sum with a taskrelated parameter derived from a pretest is utilized for time-indicated control (GO-STOP) of an external object. In experiments using untrained subjects, the system achieved control patterns within an accuracy of ±6 sec for more than 80% control.

Soft-error-immune switched-load-resistor memory cell

Various memory cell sizes that can be obtained with anticipated device size reduction are compared in Fig. 9. It is clear that a future ultra-high-speed high density bipolar RAM with sufficient soft-error immunity is possible using the new memory cell.

A Distributed Authentication Platform Architecture for Peer-to-Peer Applications

A distributed authentication platform (DAP) architecture is described that addresses the problems of fast user authentication and secure data transmission in large-scale ubiquitous networks. The user space is divided into domains, each containing an agent engine (AE), to enable rapid response to authentication requests. Dedicated channels are used for quick synchronization of the AE databases. Also described is a user-information-based model with QoS-ensured end-to-end secure-path setup. In this model, the user specifies the QoS requirement at the terminal, and the AE analyzes the information embedded in the control packet and initiates the signaling sequence to set up the path. This model is highly suitable for emerging peer-to-peer services, such as ensured-delivery e-mail, account information exchange, PDA file backup, and fixed-time data delivery. Evaluation of the AE performance demonstrated that the localization of authentication requests by using domains is an effective way of reducing the authentication processing time in a large-scale ubiquitous network. Simulated secure-path setup using three workstations demonstrated that a secure route satisfying such user specifications as priority, encryption, and bandwidth can be set up within 4.02 ms. much faster than with previous approaches.