Yahya Lakys

Compact Modeling of Perpendicular-Anisotropy CoFeB/MgO Magnetic Tunnel Junctions

Magnetic tunnel junctions (MTJs) composed of ferromagnetic layers with perpendicular magnetic anisotropy (PMA) are of great interest for achieving high-density nonvolatile memory and logic chips owing to its scalability potential together with high thermal stability. Recent progress has demonstrated a capacity for high-speed performance and low power consumption through current-induced magnetization switching. In this paper, we present a compact model of the CoFeB/MgO PMA MTJ, a system exhibiting the best tunnel magnetoresistance ratio and switching performance. It integrates the physical models of static, dynamic, and stochastic behaviors; many experimental parameters are directly included to improve the agreement of simulation with experimental measurements. Mixed simulation based on the 65-nm technology node of a magnetic flip-flop validates its relevance and efficiency for MTJ/CMOS memory and logic chip design.

Design considerations and strategies for high-reliable STT-MRAM

Abstract Benefiting from Spin Transfer Torque (STT) switching approach, second generation of Magnetic RAM (MRAM) promises low power, great miniaturization prospective (

Self-Enabled “Error-Free” Switching Circuit for Spin Transfer Torque MRAM and Logic

Spin transfer torque (STT) is one of the most promising switching approaches for magnetic tunnel junction (MTJ) nanopillars to build up innovative nonvolatile memory and logic circuits. It presents low critical current (e.g., <; 100 μA at 65 nm), simple switching scheme, and fast-speed; however, it suffers from a number of reliability issues like stochastic switching effects, process voltage temperature (PVT) variations, and erroneous reading etc. The mainstream solution is to enlarge the write pulse duration to reduce error rate, which sacrifices the speed and low power advantages. In this paper, we present a new switching circuit for STT memory and logic, allowing “error-free” as the switching operation becomes deterministic benefiting from the self-enabled mechanism. The switching power efficiency can be also improved thanks to a shorter switching duration. By using an accuracy spice model of STT-MTJ and CMOS 65 nm design-kit, mixed simulations have been performed to demonstrate its high-reliable write/read operations and evaluate its potential area, power, and speed performance.

Design of MRAM based logic circuits and its applications

As the fabrication technology node shrinks down to 90nm or below, high standby power becomes one of the major critical issues for CMOS logic circuits due to the high leakage currents. A number of non-volatile storage technologies such as FRAM, MRAM, PCRAM and RRAM and so on, are under investigation to bring the non-volatility into the logic circuits and then eliminate completely the standby power issue. Thanks to its infinite endurance, high switching/sensing speed and easy 3D integration after CMOS process, MRAM is considered as the most promising one. Numerous logic circuits based on MRAM technology have been proposed and prototyped in the last years. In this paper, we present an overview and current status of these logic circuits and their potential applications in the future.

Hardening Techniques for MRAM-Based Nonvolatile Latches and Logic

Magnetic RAM (MRAM) is considered as a promising nonvolatile memory technology for aerospace and avionic electronics thanks to its intrinsic hardness to radiation. Data is stored on the spin direction “up” and “down” of electrons instead of positive and negative charge. Thanks to its fast speed, easy integration with CMOS and infinite endurance, MRAM has been proposed to build up nonvolatile latches and logic circuits to overcome the power challenge of conventional CMOS circuits. However, they are vulnerable to single event effects (SEE) due to their CMOS peripheral circuits. Hardening techniques to mitigate SEE are described in this paper. A new design of Radhard MRAM latch is firstly presented. TMR technique is then implemented on configurable logic block (CLB) to mitigate SET on data paths. By using 65 nm design kit and an MRAM compact model, hybrid simulations have been done to demonstrate the radiation hardness and performance.

High Performance SoC Design Using Magnetic Logic and Memory

As the technolody node shrinks down to 90nm and below, high standby power becomes one of the major critical issues for CMOS highspeed computing circuits (e.g. logic and cache memory) due to the high leakage currents. A number of non-volatile storage technologies, such as FRAM, MRAM, PCRAM and RRAM, are under investigation to bring the non-volatility into the logic circuits and then eliminate completely the standby power issue. Thanks to its infinite endurance, high switching/sensing speed and easy integration on top of CMOS process, MRAM is considered as the most promising one. Numerous logic circuits based on MRAM technology have been proposed and prototyped in the last years. In this paper, we present an overview and current status of these logic circuits and discuss their potential applications in the future from both physical and architectural points of view.

Embedded MRAM for high-speed computing

As the fabrication technology node shrinks down to 90nm or below, high standby power becomes one of the major critical issues for CMOS high-speed computing circuits (e.g. logic and cache memory) due to the high leakage currents. A number of non-volatile storage technologies such as FeRAM, MRAM, PCRAM and RRAM and so on, are under investigation to bring the non-volatility into the logic circuits and then eliminate completely the standby power issue. Thanks to its infinite endurance, high switching/sensing speed and easy 3D integration after CMOS process, MRAM is considered as the most promising one. Numerous logic circuits based on MRAM technology have been proposed and prototyped in the last years. In this paper, we present an overview and current status of these logic circuits and discuss their potential applications in the future from both the physics and architecture points of view.

MRAM crossbar based configurable logic block

Spintronics-based non-volatile storage devices promise great potential to be integrated in reconfigurable circuits to overcome the major hurdles related to conventional flash and SRAM memories, such as low logic density, high standby power and long (re) boot latency. In this paper, we describe a compact design of configurable logic block based on Magnetic RAM (MRAM) crossbar architecture. The logic density can be increased greatly (~5 times) compared to conventional designs; the standby power can be nearly zero thanks to the non-volatility of MRAM. Its high speed and power efficiency (~10.4 Tera-OPS/Watt in computing mode) are also demonstrated through mixed CMOS/Magnetic spice simulations. Fully dynamic reconfiguration through context switching is also studied, which could be achieved with low area overhead.

Cognitive and encrypted communications, part 2 : A new approach to active frequency-agile filters and validation results for an agile bandpass yopology in SiGe-BiCMOS

A new theory for a 2nd-order frequency-agile filter is introduced in this paper. The center frequency of the filter is proportional to the gain of a feedback amplifier and thus can be tuned over a wide frequency range. This new theory is thereafter generalized to the nth-class leading to a center frequency proportional to (A)n/2. The resulting filters make use of the minimum passive elements for 2nd-order filters: two capacitors. Simulation results of band pass agile filters in current mode and made from second-generation current controlled conveyors (CCCIIQ) in 0.25¿m SiGe BiCMOS technology are given for n=1 and n=2. These simulation results along with results of measurements carried out on the fabricated filters entirely confirm the new approach. They also highlight the improvements to be expected for cognitive and encrypted communications.

Hardening techniques for MRAM-based non-volatile storage cells and logic

Magnetic RAM (MRAM) is considered as a promising non-volatile memory technology for aerospace and avionic electronics thanks to its intrinsic hardness to radiation. Data is stored on the spin direction “up” and “down” of electrons instead of positive and negative charge. However, MRAM-based non-volatile storage cells and logic circuits are vulnerable to Single Event Effects (SEE) due to their CMOS peripheral circuits. Hardening techniques to mitigate SEE are presented in this paper. A new design of Radhard MRAM latch is firstly presented. TMR technique is then implemented on Configurable Logic Block to mitigate SET on data paths. By using 65nm design kit and an MRAM compact model, hybrid simulations have been done to demonstrate the radiation hardness.