Yahya M. Tousi

Delay-Line-Based Analog-to-Digital Converters

We will introduce a design of analog-to-digital converters (ADCs) based on digital delay lines. Instead of voltage comparators, they convert the input voltage into a digital code by delay lines and are mainly built on digital blocks. This makes it compatible with process scaling. Two structures are proposed, and tradeoffs in the design are discussed. The effects of jitter and mismatch are also studied. We will present two 4 bit, 1 GS/s prototypes in 0.13 mum and 65 nm CMOS processes, which show a small area (0.015 mm2) and small power consumption (<2.4 mW).

A Novel CMOS High-Power Terahertz VCO Based on Coupled Oscillators: Theory and Implementation

We introduce a novel frequency tuning method for high-power terahertz sources in CMOS. In this technique, multiple core oscillators are coupled to generate, combine, and deliver their harmonic power to the output node without using varactors. By exploiting the theory of nonlinear dynamics, we control the coupling between the cores to set their phase shift and frequency. Using this method, two high-power terahertz VCOs are fabricated in a 65 nm LP bulk CMOS process. The first one has a measured output power of 0.76 mW at 290 GHz with 4.5% tuning range and the output power of the second VCO is 0.46 mW at 320 GHz with 2.6% tuning range. The output power of these signal sources is 4 orders of magnitude higher than previous CMOS VCOs and is even higher than VCOs implemented in compound semiconductors with much higher cut-off frequencies.

A 283-to-296GHz VCO with 0.76mW peak output power in 65nm CMOS

Sub-mm-Wave and terahertz frequencies have many applications such as medical imaging, spectroscopy and communication systems. CMOS signal generation at this frequency range is a major challenge due to the limited cut-off frequency of transistors and their low breakdown voltage. A recent work has demonstrated generation of high power at a fixed frequency in the sub-mm-Wave range using a harmonic oscillator [1]. However, for most applications a tunable signal source is necessary. In previous works, frequency multipliers are used as an alternative for tunable power generation above 150GHz [2]. In this work, for the first time we introduce a tunable high-power oscillator at sub-mm-Wave frequencies in low-power (LP) bulk CMOS.

A Miniature 2 mW 4 bit 1.2 GS/s Delay-Line-Based ADC in 65 nm CMOS

A delay-line-based analog-to-digital converter for high-speed applications is introduced. The ADC converts the sampled input voltage to a delay that controls the propagation velocity of a digital pulse. The output digital code is generated based on the propagation length of the pulse in a fixed time window. The effects of quantization noise, jitter, and mismatch are discussed. We show that because of the averaging mechanism of the delay-line, this structure is more power efficient in the presence of noise and mismatch in deep sub-micron CMOS. To show the feasibility of this approach, a 4 bit 1.2 GS/s ADC is designed and fabricated in 65 nm CMOS in an active area of 110 μm × 105 μm. The measured INL and DNL of the ADC are below 0.8 bits and 0.5 bits and it achieves an SNDR of 20.4 dB at Nyquist rate. This delay-line-based ADC consumes 2 mW of power from a 1.2 V supply resulting in 196 fJ/conversion step without using any calibration or post-processing.

14.6 A scalable THz 2D phased array with +17dBm of EIRP at 338GHz in 65nm bulk CMOS

In traditional phased arrays as the number of rows and columns increases, the complexity of array connections and phase shifters becomes a major obstacle. This challenge is even more detrimental at mm-Wave and THz frequencies where conductive loss, undesired couplings, phase/gain mismatch, and high power consumption are among many adverse effects of such lengthy connections. To address this issue, this work presents a novel scalable system for THz signal generation and radiation. Figure 14.6.1 shows the architecture consisting of a 2-D array of coupled oscillating elements. Each oscillator with its antenna forms a small THz radiator. While independently radiating, each element is also unidirectionally connected to its neighboring elements in both horizontal and vertical directions through variable phase shifters, ψrow and ψcol, respectively. This network is inherently scalable because it only relies on couplings with the nearest neighbors and there is no high-frequency global routing to any oscillator. The purpose of this topology is twofold: first to synchronize all the oscillators to a single frequency and next, to set a desired phase shift between the adjacent elements (Δφrow and Δφcol). We can show that by employing this particular coupling structure only a small subset of all the theoretical coupling modes are physically stable. By proper control of the couplings one can ensure the system settles into the desired coupling mode [1].

7.2 A 28GHz 32-element phased-array transceiver IC with concurrent dual polarized beams and 1.4 degree beam-steering resolution for 5G communication

Next-generation mobile technology (5G) aims to provide an improved experience through higher data-rates, lower latency, and improved link robustness. Millimeter-wave phased arrays offer a path to support multiple users at high data-rates using high-bandwidth directional links between the base station and mobile devices. To realize this vision, a phased-array-based pico-cell must support a large number of precisely controlled beams, yet be compact and power efficient. These system goals have significant mm-wave radio interface implications, including scalability of the RFIC+antenna-array solution, increase in the number of concurrent beams by supporting dual polarization, precise beam steering, and high output power without sacrificing TX power efficiency. Packaged Si-based phased arrays [1–3] with nonconcurrent dual-polarized TX and RX operation [2,3], concurrent dual-polarized RX operation [3] and multi-IC scaling [3,4] have been demonstrated. However, support for concurrent dual-polarized operation in both RX and TX remains unaddressed, and high output power comes at the cost of power consumption, cooling complexity and increased size. The RFIC reported here addresses these challenges. It supports concurrent and independent dual-polarized operation in TX and RX modes, and is compatible with a volume-efficient, scaled, antenna-in-package array. A new TX/RX switch at the shared antenna interface enables high output power without sacrificing TX efficiency, and a t-line-based phase shifter achieves <1° RMS error and <5° phase steps for precise beam control.

A High-Power and Scalable 2-D Phased Array for Terahertz CMOS Integrated Systems

This work introduces a 2-D phased array architecture that is suitable for high power radiation at mm-Wave and Terahertz frequencies. We address the challenge of signal generation above the cut-off frequency of transistors by presenting a radiation method based on the collective performance of a large number of synchronized sources. As theory shows, both frequency locking/tuning and beam steering can be independently achieved by manipulating the local coupling between the nearest neighbors. This control method results in a dynamical network that is insensitive to array dimensions and is scalable to the point that can achieve a level of output power and spectral purity beyond the reach of conventional sources. To demonstrate the concept, we implement a 4 ×4 version of this phased array at 340 GHz using a 65 nm bulk CMOS process. The paper presents the design and implementation of the oscillators, couplings and the integrated antennas. The measured results at 338 GHz reveal a peak equivalent isotropically radiated power (EIRP) of +17.1 dBm and a phase noise of -93 dBc/Hz at the 1 MHz offset frequency. This chip presents the first fully integrated terahertz phased array on silicon. Furthermore, the output power is higher than any lens-less silicon-based source above 200 GHz and the phase noise is lower than all silicon radiating sources above 100 GHz.

A 1mW 4b 1GS/s delay-line based analog-to-digital converter

In this paper we introduce a novel Analog-to-Digital architecture for high speed applications that is compatible with digital CMOS and surpasses the issues with traditional voltage conversion techniques. The quantization method is based on the delay-to-digital concept as a means to quantize a variable delay line. A 4bit 1GS/s ADC with 1mW power consumption is designed in 65nm CMOS based on the proposed architecture. The new architecture is highly scalable with CMOS technology and because of its delay-line-based core, the ADCs performance enhances with further CMOS scaling and provides a promising method for the trend toward more digital implementation of circuits.

A Ka-band digitally-controlled phase shifter with sub-degree phase precision

We present a passive digital-to-phase converter with sub-degree phase precision for phased array frontends. The phase tuning approach is based on manipulating the electromagnetic properties of an artificially constructed transmission line. By simultaneously controlling dispersion, characteristic impedance, and loss across the structure, the phase shifter minimizes phase imprecisions while ensuring a flat amplitude response across different phase settings. The chip prototype is fabricated in a 130nm SiGe BiCMOS process, occupies an area of 0.18mm2, and consumes no power. The insertion loss is -9.3 dB ± 0.25 dB at 28 GHz. The phase control operates with 4.75 degree steps while maintaining an RMS phase error of 0.6 degrees across multiple chips and temperatures, demonstrating the best phase and amplitude accuracy when compared to state-of-the-art integrated microwave and mm-wave phase shifters.

2-D Electrical Interferometer: A Novel High-Speed Quantizer

In this paper, we propose a 2-D electrical interferometer as a means of high-speed data conversion. The structure is based on wave propagation in 2-D LC lattices. We will discuss the principle behind this technique, which exploits wave propagation and medium manipulation in order to take advantage of different interference patterns. This method of quantization is based on passive LC lattices that can operate at very high frequencies on a conventional CMOS process. We analyze different properties of the structure and propose the design methodology. To show the feasibility of this approach, we design a 20-GS/s 4-bit quantizer consuming 194 mW for quanization and 943 mW for an analog memory. There is good agreement between analysis and simulation.