Yajuan He

Digital Error Corrector for Phase Lead-Compensated Buck Converter in DVS Applications

Modern low-power system on a chip needs direct current converter with dynamic voltage scaling (DVS) ability for core power supply. The converter output should be accurate voltage across the full load current and voltage scaling range. An integrated buck converter for DVS application is proposed in this brief. Voltage mode phase lead compensation is implemented in the converter, with much smaller passive components than conventional type-III compensation. To improve accuracy, the output voltage error accompanied with load current and reference voltage caused by finite loop gain in analog control loop is corrected by the digital error corrector. The output voltage is compared by two comparators whose threshold voltage is about 10 mV above and below the reference voltage, respectively. The duty cycle is slightly adjusted by finite state machine according to outputs of the two comparators. Experimental results show that the converter is well regulated over an output range of 0.7-1.8 V, with step voltage of 25 mV. When load current suddenly changes between 170 and 500 mA, the overshoot and undershoot voltage are 32 and 50 mV, respectively. Load regulation is maintained about 1% throughout the full load range. The voltage error is within ±10 mV in the voltage scaling range.

A miniature high-efficiency fully digital adaptive voltage scaling buck converter

A miniature high-efficiency fully digital adaptive voltage scaling (AVS) buck converter is proposed in this paper. The pulse skip modulation with flexible duty cycle (FD-PSM) is used in the AVS controller, which simplifies the circuit architecture (<170 gates) and greatly saves the die area and the power consumption. The converter is implemented in a 0.13-μm one-poly-eight-metal (1P8 M) complementary metal oxide semiconductor process and the active on-chip area of the controller is only 0.003 mm2, which is much smaller. The measurement results show that when the operating frequency of the digital load scales dynamically from 25.6 MHz to 112.6 MHz, the supply voltage of which can be scaled adaptively from 0.84 V to 1.95 V. The controller dissipates only 17.2 μW, while the supply voltage of the load is 1 V and the operating frequency is 40 MHz.

A fast and energy efficient binary-to-pseudo CSD converter

The canonical signed digit (CSD) coding is widely used in digital arithmetic operations due to its property that there is no adjacent nonzero digits in the encoded numbers. However, the benefits of the CSD coding may be faded because of the recursive conversion process from the binary representations. This paper presents a novel pseudo CSD coding method, which takes the merits of CSD, while simplifies the conventional conversion process. The simulation results indicate that the proposed converter can achieve at least 31.8% speed improvement and 42.9% energy reduction for a 16-bit binary operand at 1.2V in a 0.13-μm CMOS technology. It could run even faster than the competitors when the operand length increases.

A pulse skipping modulation with adaptive duty ratio in buck converter application

A pulse skipping modulation (PSM) with adaptive duty ratio (APSM) in buck converter application is presented in this paper. The output voltage of converter is regulated by the APSM controller generating control pulse with multiple duty ratios. The duty ratio is approximately proportional to the square root of the voltage error between output voltage of converter and reference voltage. The experimental results and simulation are well consistent with theoretical analysis. The duty ratio can vary adaptively with the variance of voltage error and load. The APSM modulation technology can regulate output voltage slightly and improve ripple of output voltage especially in light load.

Design of a power optimized 1024-point 32-bit single precision FFT processor

Fourier transform is the basic operation between time and frequency domain transformation. As a key operation of digital signal processing system, Fast Fourier Transform (FFT) is widely used in many fields such as communication, biomedical signal processing and image processing, which require a high precision of processed signal. To meet the requirement, the floating point number can be used to improve the signal quantization noise ratio (SQNR) greatly. In this paper, we proposed a power optimized 1024-point high precision FFT processor with 32-bit single precision floating point number for both input and output. Simulation results show that the proposed FFT works at 1.2 V, consumes 17.6 mW with a 0.13 μm CMOS technology. Its SQNR can reach 97 dB, which is ~2× higher than the conventional design when maintaining the same power consumption. In the meanwhile, it gains ~99% power reduction when maintaining the same SQNR.

A full differential Enhanced Pseudo-Type III compensator for DC-DC converter

A novel full differential Enhanced Pseudo-Type III (EPT3) compensator for DC-DC converter is presented in this paper. The proposed EPT3 compensator achieves same transfer function as conventional Type III compensator by combination of voltages compensated by Phase Lead Compensator and compensated by Low-Pass filter. Besides, the compensator utilizes full differential configuration to suppress the common mode noise and avoid crosstalk from the ground, which makes the compensator suitable for integration in Power Management Unit (PMU). A buck converter with this compensator is designed in 0.13μm CMOS process. Simulation results show recover time of 13μs for load transient at 400mA step and the phase margin of 68° with much smaller passive components (C=12pF, R=500kΩ) than Pseudo Type III compensator.

A high PVT tolerance TDC with symmetrical Vernier delay ring

A novel Vernier delay ring (VDR) used in time-to-digital converter (TDC) is presented in this paper. This Vernier delay ring is perfectly symmetrical compared with traditional Vernier ring by introducing a set of buffers and loads. It significantly reduces the affects of circuit parameters on the process, supply voltage and temperature (PVT) variations. This circuit also inherits the merits of the traditional Vernier ring time-to-digital converter (VRTDC), such as high resolution, large detectable rang. The proposed Vernier Delay Ring TDC achieves a 0.004ps/°C temperature coefficient of time resolution in 0.13μm CMOS technology.

Pulse skipping width modulation mode in buck converter application

In order to make the buck converter obtain smaller voltage ripple and higher efficiency at the same time, the pulse skipping width modulation (PSWM) mode in buck converter application is proposed in this paper. This novel controlling mode combines the advantage of pulse skipping modulation (PSM) with improving voltage ripple especially in lighter load and pulse width modulation (PWM) having higher conversion efficiency in heavy load. The proposed circuit is simulated in a 0.18µm standard CMOS process. The simulation results show that, the output voltage of converter can be well regulated in 1.2V, and the output voltage ripple is about 1mV and 4mV in light-load and heavy-load, respectively. The change of output voltage is about 2 mV and setting time is about 28µs when load current changes from 30mA to 70mA.

A minimum energy point tracking converter based on constant energy pulse

To reduce the energy dissipation of the digital load, a minimum energy point tracking (MEPT) converter based on constant energy pulse (CEP) is proposed in this paper. Controlling the numbers of CEP, and based on slope tracking algorithm, the function of tracking the minimum energy point of the digital load can be realized. The structure of the proposed MEPT converter, the generating mechanism of the CEP and the tracking algorithm of MEPT are given out in this paper. The proposed converter can greatly decrease the energy dissipation of digital load. The layout and simulation results of the MEPT converter based on a 0.13μm standard CMOS technology are also given.

Hybrid pseudo type-III compensated AVS-enabled regulator for energy-efficient computing

Adaptive voltage scaling (AVS) regulator is proposed in the paper. Based on hybrid pseudo type-III (HPT3) compensator, the digital load is powered adaptively with operation frequency. Consequently, the power dissipation of digital circuit is reduced significantly, especially for lower operation frequency. The proposed HPT3 compensator consists of analog phase lead (APD) compensation path and delay integration (DPI) compensation path. The output voltage and the delay of critical path are feed to APD path and DPI path, respectively. The delay of critical path is then clamped to one clock cycle by setting output voltage adaptively. The proposed AVS-enabled regulator is designed with 0.13μm CMOS process. Simulation results show that the converter is well regulated over external clock frequency range of 20MHz-300MHz. The overshoot and undershoot voltage for load transient response of 400mA are smaller than 35mV and 30mV, respectively. And the recovery time is less than 3μs. The frequency tracking speed from 20MHz to 100MHz is 5μs. Compared to fixed supply voltage and DVS, up to 84.6% and energy consumption is saved by using the proposed AVS-enabled regulator.