Yao-Ching Ku

An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling

This letter introduces an analytical model to represent line-edge roughness (LER) effects on both off-state leakage and drive current for sub-100-nm devices. The model partitions a given device into small unit cells along its width, each unit cell assumes a constant gate length (i.e., cells width is small compared to LER spatial frequency). An analytical model is used to represent saturated threshold voltage dependency on the unit cells gate length. Using this technique, an efficient and accurate model for LER effects (through V/sub ts/ variations) on off-state leakage and drive current is proposed and experimentally validated using 193 and 248 nm lithography for devices with 80-nm nominal gate lengths. Assuming that the deviation from the ideal 0-LER case remains constant from generation to generation, the model predicts that 3 nm or less LER is required for 50-60-nm state-of-the-art devices in the 0.1-/spl mu/m technology node. Based on data presented, we suggest that the LER requirement for this technology node is attainable with an alternated phase-shift type of patterning process.

Use of a pi‐phase shifting x‐ray mask to increase the intensity slope at feature edges

In x‐ray lithography at deep submicron and sub‐100‐nm linewidths, the effects of diffraction are not negligible. We have investigated the possibility of improving the slope of the irradiance profile at feature edges by using an absorber that produces a pi‐phase shift in addition to about 10 dB attenuation. Both numerical simulation and experimental modeling at a longer wavelength (365 nm) were used. These show that the irradiance profile at the edge of features is steeper when using a pi‐phase shifting mask. For gold, the condition of pi‐phase shift and 10 dB attenuation occurs when the wavelength is 1.15 nm and the thickness is 290 nm; and for tungsten at a wavelength of 1.3 nm and a thickness of 275 nm. X‐ray masks made with the proper phase‐shift and attenuation yield an increased slope at feature edges which should result in improved process latitude. The phase‐shifting scheme introduced here differs from those previously described, and applies to patterns of arbitrary geometry, including isolated lines and spaces.

In situ stress monitoring and deposition of zero-stress W for x-ray masks

We have developed and tested a computer‐controlled system for monitoring in situ the stress of tungsten sputter deposited onto x‐ray mask membranes. This system allows us to achieve zero stress (i.e., <5×107 dyn/cm2) tungsten. The stress is monitored via the resonant frequency of the x‐ray mask membrane which changes during deposition due to W stress, mass loading, and temperature rise. Differences in W stress give rise to differences in curvatures of the plot of resonant frequency versus W thickness. This effect can be used to ensure that a film will have stress below 1×108 dyn/cm2 and can also be the basis of an automated closed‐loop, in situ stress control system.

Fabrication and characterization of high-flatness mesa-etched silicon nitride x-ray masks

To realize a technology for x‐ray nanolithography (<100 nm features), which is compatible with manufacturing, a number of mask design requirements must be met that are unrelated to patterning, repair, and alignment. These include high‐flatness membranes and support structures so that mask‐wafer gaps less than 10 μm can be achieved without risk of damage, and a rigid mask frame to avoid problems of distortion during handling. The membrane material should be compatible with semiconductor‐processing, possess high strength, be radiation hard, and be transparent to light for alignment purposes. Details of a mask architecture that meets these requirements will be described.

Patterning effect and correlated electrical model of post-OPC MOSFET devices

Accurate simulation of todays devices needs to account for real device geometry complexities after the lithography and etching processes, especially when the channel length shrinks to 65-nm and below. The device performance is believed to be quite different from what designers expect in the conventional IC design flow. The traditional design lacks consideration of the photolithography effects and pattern geometrical operations from the manufacturing side. In to order obtain more accurate prediction on circuits, an efficient approach to estimate nonrectangular MOSFET devices is proposed. In addition, an electrical hotspot criterion is also proposed to investigate and verify the manufacturability of devices during patterning processes. This electrical rule criterion will be performed after the regular Design Rule Check (DRC) or Design for Manufacturing (DFM) rule check. Photolithography and industrial-strength SPICE model are taken into consideration to further correlate the process variation. As a result, the correlation between process-windows and driving current variation of devices will be discussed explicitly in this paper.

Contrast improvement with balanced diffusion control of PAG and PDB

For semiconductor manufacturing of k1<0.3 half pitch, immersion lithography is still indispensable for process development and production. As the minimum feature size reaches the resolution limit, many resolution enhancement techniques and processes are developed to meet the stringent imaging requirements. Since the optical contrast is not sufficient for low-k1 application, the optimizing conditions for DOF, MEEF, LWR, 2D features, top-view profile, and defect become more challenging than ever for manufacturing. The low-k1 induced poor ADI (after development inspection) end-to-end profile is deleterious to pattern fidelity that may further impact the AEI (after etching inspection). From a previous study, the photo-decomposed base (PDB) has been proven effective in enhancing the resist contrast and improving the DOF from conventional quenchers. In this paper, we study its further improvement on litho performance by controlling the diffusion lengths of the PAG and the PDB. We split the polarity and size of the PAG and PDB to control the diffusion length. The top view profile is improved from rounding to vertical if a longer diffusion length of the PDB is selected. The scattering bar printing window can also be improved in such a condition. If the PAG and the PDB have better matching controls, the MEEF, LWR, CDU, and end-to-end top view profile are improved as shown in Fig.1.

Sub‐100‐nm x‐ray mask technology using focused‐ion‐beam lithography

In the past, nearly all x‐ray nanolithography (i.e., sub‐100‐nm linewidths) employed the CK x‐ray line at 4.5 nm. This, in turn, necessitated near‐zero gaps (to avoid diffraction) and carbonaceous masks (e.g., polyimide, which is subject to distortion). In order to use x‐ray replication in the fabrication of multilevel devices and circuits that cover large areas (∼a few cm2) and have feature sizes well below 100 nm, we have turned to the CuL line at 1.3 nm. Masks consist of 1–1.5 μm thick Si or Si3N4 membranes and Au absorber patterns, 200 nm thick, which provide 10 db contrast. Focused‐ion‐beam‐lithography (FIBL) with Be++ ions at 280 keV was used to produce quantum‐effect‐device patterns with minimum linewidths of ∼50 nm. These were replicated using the CuL line, indicating that photoelectrons are not a serious problem. The FIBL process [exposure of 300 nm‐thick polymethylmethacrylate (PMMA), followed by Au electroplating] is high yield and much simpler than a trilevel electron‐beam‐lithography process ...

Improving on-product performance at litho using integrated diffraction-based metrology and computationally designed device-like targets fit for advanced technologies (incl. FinFET)

In order to meet current and future node overlay, CD and focus requirements, metrology and process control performance need to be continuously improved. In addition, more complex lithography techniques, such as double patterning, advanced device designs, such as FinFET, as well as advanced materials like hardmasks, pose new challenges for metrology and process control. In this publication several systematic steps are taken to face these challenges.

Fabrication and testing of 0.1‐μm‐linewidth microgap x‐ray masks

A technology has been developed for the printing of 0.1‐μm‐linewidth patterns using a ‘‘microgap,’’ out‐of‐contact scheme for x‐ray nanolithography (as opposed to zero‐gap electrostatic contact). Mask‐to‐wafer gaps of ∼5 μm are maintained by the use of gap‐setting aluminum studs fabricated onto the front surface of the mask mesa rim. X‐ray mask blanks are fabricated from silicon wafers coated with low‐stress, silicon‐rich low‐pressure chemical vapor deposition SiNx. The resulting 1–2‐μm‐thick 6×108 dyn/cm2 stress membranes exhibit extreme strength. A novel aluminum‐stencil etching procedure—which includes three CF4 RIE and two KOH etching steps—is used to define the mask membrane and ‘‘mesa’’ structure. Mask absorber pattern fabrication is performed by focused‐ion‐beam lithography (FIBL) and gold electroplating. We present details of the mask fabrication procedure and the results of testing these masks with x rays from a laboratory CuL (λ=1.34 nm) electron bombardment source and a commercial pulsed laser‐...

Thin-film optimization strategy in high numerical aperture optical lithography, part 1: principles

The functional dependence of a resist critical dimension (CD) with respect to resist thickness for a general absorptive thin-film stack in the case of oblique incidence is derived analytically with the rigorous electromagnetic theory. Based on obtained results, we discuss those thin-film effects related to CD control, such as the swing effect, bulk effect, etc., especially in the regime of high numerical aperture optical lithography.