Yoetsu Nakazawa

A read-static-noise-margin-free SRAM cell for low-V/sub dd/ and high-speed applications

A read-static-noise-margin-free SRAM cell consists of seven transistors, several of which are low-V, NMOS transistors used to achieve both low-V/sub dd/ and high-speed operation. A 64 kb SRAM macro is fabricated in 90 nm CMOS technology. Both a minimum V/sub dd/ of 440 mV and a 20 ns access time with a 0.5 V supply are obtained.

A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power motion estimation and clocking

A 1.5-W single-chip MPEG-2 MP@ML real-time video encoder large scale integrated circuit (LSI) has been developed. To form an MPEG-2 encoder system, we employ two 16-Mb synchronous DRAMs, a microprocessor unit (MPU), and an audio encoder LSI. Owing to a two-step hierarchical search scheme and a novel adaptive search window scheme, the search range of motion estimation is -48/+47 horizontal and -96/+15.5 vertical, and the pseudo search range, which is the size when the location of the search window is adaptively shifted, is -96/+95 horizontal and -32/+31.5 vertical. We have also developed low-power clocking techniques, i.e., demand-clock controller, local-clock controller, and low-power flip-flops, which can eliminate waste of power in clocking. We have successfully fabricated these new designs as a low-power single-chip MPEG-2 encoder LSI. The operating frequency except for a synchronous DRAM interface unit and a video in/out unit is 54 MHz. The supply voltage to the first and second search engines in a motion estimation unit can be successfully lowered to 2.5 V and the others are 3.3 V. Into a 12.45/spl times/12.45 mm/sup 2/ chip with 0.35-/spl mu/m CMOS and triple-metal layer technology are integrated 3.1 M transistors.

A dynamically reconfigurable logic engine with a multi-context/multi-mode unified-cell architecture

Reconfigurable logic LSIs, such as FPGAs, have been perceived as devices for prototyping and emulation. As the size and speed of FPGAs rapidly increase, however, they have begun to be used in /spl mu/P-based systems as reconfigurable accelerators. The idea is to achieve both hardware efficiency and software programmability by dynamically reconfiguring FPGAs. This idea, reconfigurable computing, provides an attractive solution especially for media/network-centric applications. Various types of reconfiguration scenarios in such applications, however, require logic LSIs to significantly enhance reconfigurability in three respects: (1) agility-reconfiguration may need to take place in very short intervals, say within a hundred /spl mu/P instructions; (2) controllability-reconfiguration may be controlled from an external /spl mu/P or by itself; (3) flexibility-reconfiguration target may be arbitrarily positioned and irregularly shaped. The dynamically reconfigurable logic engine (DRLE) prototype described meets this challenge.

A 7.68 GIPS 3.84 GB/s 1W parallel image processing RAM integrating a 16 Mb DRAM and 128 processors

A parallel image processing RAM (PIP-RAM) integrates a 16 Mb DRAM and 128 processor elements (PEs) on a single chip in 64 Mb DRAM process technology. There are three general design requirements when integrating DRAMs and processors onto a single chip: high-data-rate random access, low-power dissipation, and efficiently synchronized DRAM and processor. The PIP-RAM employs three circuit techniques in response to these requirements: (1) a paged-segmentation accessing (PSA), (2) a clocked low-voltage-swing differential-charge-transfer (CLD), and (3) a multiphase synchronization DRAM control (MSD) that uses a multiple-stage PLL. Large memory capacity and high-data-rate random access achieved by these techniques make the PIP-RAM suitable for image processing of large-scale, full-color pictures.

A Circuit for Determining the Optimal Supply Voltage to Minimize Energy Consumption in LSI Circuit Operations

We have developed a circuit for determining an optimal supply voltage, VOPT, for which energy consumption will be minimized in devices suffering from high-leakage. This VOPT is determined on the basis of a trade-off between power consumption and operation time. Experimental results with a 90-nm CMOS device indicate that the proposed circuit successfully determines VOPT with high accuracy. VOPT operations with power gating at 40 MHz, and where VDD = 0.67 V, results in an energy reduction of 52.8% over that achieved with DVFS alone at 5 MHz (1/20 of maximum operational frequency). Further, we propose a scheme for suppressing determination error, one that results in voltage error of less than 50 mV.

Monitoring scheme for minimizing power consumption by means of supply and threshold voltage control in active and standby modes

This paper describes a newly developed monitoring scheme for minimizing power consumption by means of supply voltage V/sub DD/ and threshold voltage V/sub TH/ dynamic control in active and standby modes. In the active mode, on the basis of delay monitoring results, either V/sub DD/ control or V/sub TH/ control is selected to avoid any oscillation problem between them. Switching current I/sub SW/ and leakage current I/sub LEAK/ are monitored, and V/sub TH/ is adjusted so as to maintain that ratio known to indicate minimum power consumption. In the standby mode, the precision of optimum body bias monitoring is improved by taking into consideration the effects of lowered V/sub DD/ and gate-oxide leakage current. Experimental results with a 90-nm CMOS device indicate that the proposed scheme results in successful I/sub SW//I/sub LEAK/ ratio maintenance and successful detection of optimum body bias conditions (I/sub OFF/ = I/sub SUB/ (= GIDL + I/sub GB/)) to within 20% of actual minimum leakage current values.

Compression/decompression DRAM for unified memory systems: a 16 Mb, 200 MHz, 90% to 50% graphics-bandwidth reduction prototype

Describes a unified memory system containing CompressDRAMs. The system is based on a Synclink-type packet-oriented DRAM architecture. CompressDRAMs are connected along the main memory bus, just as other conventional DRAMs are. A frame buffer is allocated on a CompressDRAM, and the graphics data is transferred in compressed form from/to the frame buffer. Here the memory bus consists of unidirectional command link and bi-directional data link, both at 200MHz, double data rate. A 40b request packet is issued from a memory/graphics controller to a target DRAM or CompressDRAM using 10b CA of Command Link, while a variable length data packet is transmitted over 16b DQ of Data Link (800MB/s peak bandwidth). A unidirectional READY signal is newly introduced to synchronize the controller and the CompressDRAMs.

64 Mb 6.8 ns random ROW access DRAM macro for ASICs

With the emerging huge demand for multimedia applications, even personal computers have come to require enhanced memory systems, especially for 3D graphics, MPEG encoding, and image/voice recognition. While the large memory bandwidth of Rambus DRAMs and Synchronous DRAMs offers high-speed data transfer and large capacity, they fall short in terms of low latency. Despite the efforts made by many programmers to circumvent the effects of the high latency of DRAM access, memory access instructions continue to accumulate, which limits system performance. The many conditional branch/jump operations of mixed multi-media applications (e.g., MPEG-4), for example, make such attempts at circumvention almost completely impossible. In fact, both lower random access latency and larger bandwidth are actually more pressing requirements for the latest memory systems. In response to this situation, this 6.8ns random ROW access DRAM macro has 64Mb capacity and 9.1ns complete random access cycle. This high-speed random access DRAM macro for ASICs, is to be combined with logics for 3D graphics, MPEG encoding, and image/voice recognition to create compact, low-power, high-performance LSIs for multimedia applications.

Fast voltage control scheme with adaptive voltage control steps and temporary reference voltage overshoots for dynamic voltage and frequency scaling

We have developed a voltage control scheme to reduce control time using a delay monitor and step-by-step supply-voltage control. With this scheme, voltage control steps are adaptively controlled, and there are temporary overshoots in the reference voltage. Experimental results with a 65-nm CMOS device indicate that the adaptive voltage control steps successfully reduce the voltage control time by about 35 % over that with fixed step. Simulation results indicate that temporary reference voltage overshoots reduce control time by more than 50%. The combination of these schemes is also effective for control time reduction.

An Optimal Supply Voltage Determiner Circuit for Minimum Energy Operations

We have developed a circuit for determining an optimal supply voltage, VOPT for which energy consumption in circuit operations will be minimized in devices suffering from high-leakage. This VOPT is determined on the basis of a trade-off between power consumption and delay time. Experimental results with a 90-nm CMOS device indicate that the proposed circuit successfully determines VOPT within 3% of actual minimum energy consumption. VOPT operations with power gating at 40 MHz, and where VDD=0.67 V, results in an energy reduction of 52.8% over that achieved with DVFS alone at 5 MHz (1/20 of maximum operational frequency).