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Dive into the research topics where Yasuhiko Matsunaga is active.

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Featured researches published by Yasuhiko Matsunaga.


international solid-state circuits conference | 2011

A 151mm 2 64Gb MLC NAND flash memory in 24nm CMOS technology

Koichi Fukuda; Yoshihisa Watanabe; Eiichi Makino; Koichi Kawakami; Jumpei Sato; Teruo Takagiwa; Naoaki Kanagawa; Hitoshi Shiga; Naoya Tokiwa; Yoshihiko Shindo; Toshiaki Edahiro; Takeshi Ogawa; Makoto Iwai; Osamu Nagao; Junji Musha; Takatoshi Minamoto; Kosuke Yanagidaira; Yuya Suzuki; Dai Nakamura; Yoshikazu Hosomura; Yuka Furuta; Mai Muramoto; Rieko Tanaka; Go Shikata; Ayako Yuminaka; Kiyofumi Sakurai; Manabu Sakai; Hong Ding; Mitsuyuki Watanabe; Yosuke Kato

NAND flash memories are now indispensable for our modern lives. The application range of the storage memory devices began with digital still cameras and has been extended to USB memories, memory cards, MP3 players, cell phones including smart phones, netbooks, and so on. This is because higher storage capacity and lower cost are realized through means of technology scaling every year. Emerging markets, such as solid-state drives (SSDs) and data-storage servers, require lower bit cost, higher program and read throughputs, and lower power consumption


IEEE Journal of Solid-state Circuits | 2012

A 151-mm

Koichi Fukuda; Yoshihisa Watanabe; Eiichi Makino; Koichi Kawakami; Jumpei Sato; Teruo Takagiwa; Naoaki Kanagawa; Hitoshi Shiga; Naoya Tokiwa; Yoshihiko Shindo; Takeshi Ogawa; Toshiaki Edahiro; Makoto Iwai; Osamu Nagao; Junji Musha; Takatoshi Minamoto; Yuka Furuta; Kosuke Yanagidaira; Yuya Suzuki; Dai Nakamura; Yoshikazu Hosomura; Rieko Tanaka; Mai Muramoto; Go Shikata; Ayako Yuminaka; Kiyofumi Sakurai; Manabu Sakai; Mitsuyuki Watanabe; Yosuke Kato; Toru Miwa

A 64-Gb MLC (2 bit/cell) NAND flash memory with the highest memory density to date as an MLC flash memory, has been successfully developed. To decrease the chip size, 2-physical-plane configuration with 16 KB wordline-length, a new bit-line hook-up architecture, and a top-metal-congestion-free optimized peripheral circuit floor plan, are introduced. As a result, 151 mm2 die size with an excellent 79% cell area efficiency is achieved. Newly introduced precharge detect algorithm and smart precharge algorithm improve program throughput by 10%. 14 MB/s program throughput is obtained, which is comparable or even higher performance than NAND flash memories reported in the previous 30 nm technology generation. The proposed smart precharge algorithm reduces program operation current by 6%, and 25 mA operation current with 16 KB programming is achieved. Moreover, a high-speed asynchronous DDR interface is incorporated and 266 MB/s data transfer is achieved.


international electron devices meeting | 2009

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Wataru Sakamoto; Toshitake Yaegashi; Takayuki Okamura; Takayuki Toba; Ken Komiya; Kiwamu Sakuma; Yasuhiko Matsunaga; Yutaka Ishibashi; Hidenobu Nagashima; Motoki Sugi; Nobuhito Kawada; Masashi Umemura; Masaki Kondo; Takashi Izumida; Nobutoshi Aoki; Toshiharu Watanabe

20nm-node planar MONOS cell which has improved reliability is developed. Extremely wide program/erase Vth window and good retention characteristics after cycling stress are obtained by buried charge cell structure. Moreover, Vth shift by interference between adjacent cells has smaller dependence on the cell-cell space than Vth window improvement when the half pitch is constant. These results show that the buried charge planar MONOS cell is suitable for Flash memory with 20nm-node and beyond.


Archive | 2002

64-Gb 2 Bit/Cell NAND Flash Memory in 24-nm CMOS Technology

Yasuhiko Matsunaga; Toshitake Yaegashi; Fumitaka Arai; Riichiro Shirota


Archive | 2006

Reliability improvement in planar MONOS cell for 20nm-node multi-level NAND Flash memory and beyond

Kikuko Sugimae; Masayuki Ichige; Fumitaka Arai; Yasuhiko Matsunaga; Atsuhiro Sato


Archive | 2003

NAND type non-volatile semiconductor memory device

Fumitaka Arai; Yasuhiko Matsunaga; Makoto Sakuma; Riichiro Shirota; Akira Shimizu


Archive | 2005

Nonvolatile semiconductor memory and fabrication method for the same

Naohisa Iino; Yasuhiko Matsunaga; Fumitaka Arai


Archive | 2006

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING IMPROVED GATE ELECTRODE

Makoto Sakuma; Yasuhiko Matsunaga; Fumitaka Arai; Kikuko Sugimae


Archive | 2003

Non-volatile semiconductor memory and method for fabricating a non-volatile semiconductor memory

Fumitaka Arai; Riichiro Shirota; Toshitake Yaegashi; Akira Shimizu; Yasuhiko Matsunaga; Masayuki Ichige; Hisataka Meguro


Archive | 2003

Semiconductor device with double barrier film

Fumitaka Arai; Yasuhiko Matsunaga; Makoto Sakuma; Riichiro Shirata; 誠 佐久間; 泰彦 松永; 理一郎 白田; 史隆 荒井

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