Toshitake Yaegashi

A novel high-density 5F/sup 2/ NAND STI cell technology suitable for 256 Mbit and 1 Gbit flash memories

This paper describes a novel high density 5F/sup 2/ (F: feature size) NAND STI cell technology which has been developed for a low bit-cost flash memories. The extremely small cell size of 0.31 /spl mu/m/sup 2/ has been obtained for the 0.25 um design rule. To minimize the cell size, a floating gate is isolated with a shallow trench isolation (STI) and a slit formation by a novel SiN spacer process, which has made it possible to realize a 0.55 /spl mu/m-pitch isolation at a 0.25 /spl mu/m design rule. Another structural feature integral to the cell and its small size is the borderless bit-line and source-line contacts which are self-aligned with the select-gate. The proposed NAND cell with the gate length of 0.2 /spl mu/m and the isolation space of 0.25 /spl mu/m shows a normal operation as a transistor without any punch-through. Therefore, this 5F/sup 2/ NAND STI cell technology is essential to realize a low cost flash memories of 256 Mbit and 1 Gbit for mass-storage applications.

A self-aligned STI process integration for low cost and highly reliable 1 Gbit flash memories

This paper describes a self-aligned Shallow Trench Isolation (STI) process integration to realize a low cost and high reliability 1 Gbit NAND flash memory. Peripheral low voltage CMOS transistors, high voltage transistors and small 5F/sup 2/ memory cells can be fabricated at the same time by using the self-aligned STI process. The advantages are as follows. (1) The number of process steps is reduced to 60% in comparison with a conventional process. (2) a high reliability of the gate oxide is realized even for high voltage transistors because the gate electrode does not overlap the trench corner. (3) A tight distribution of the threshold voltages (2.0 V) in a 2 Mbit memory cell array is achieved due to a good uniformity of the channel width in the self-aligned STI cells. Therefore this process integration combines a low cost with a high reliability for a manufacturable 1 Gbit flash memory.

A 120mm 2 16Gb 4-MLC NAND Flash Memory with 43nm CMOS Technology

NAND flash memory use in digital still cameras and cellular phones is driving demand for larger-capacity storage. Moreover, NAND flash has the potential to replace HDDs. To achieve larger capacity while maintaining low cost per bit, technical improvements in feature size and area reduction are essential. To meet the stringent requirements, we develop a 16 Gb 4-level NAND flash memory in 43 nm CMOS technology. In 43 nm generation, gate-induced drain leakage (GIDL) influences the electrical field on both sides of NAND strings. GIDL causes severe program disturb problems to NAND flash memories. To avoid GIDL, two dummy wordlines (WL) on both sides of NAND strings are added. This is effective because the dummy gate voltages, are selected independent of the program inhibit voltage.

A High-performance Multi-level NAND Flash Memory with 43nm-node Floating-gate Technology

Multi-level programming is demonstrated with 43 nm-node NAND floating-gate megabit cells for the first time, by thinning an inter-gate dielectric film to less than 13 nm. 43 nm-node cobalt-silicide control-gate and copper bit-line technologies are developed to achieve low resistances of the word lines and bit lines.

Reliability improvement in planar MONOS cell for 20nm-node multi-level NAND Flash memory and beyond

20nm-node planar MONOS cell which has improved reliability is developed. Extremely wide program/erase Vth window and good retention characteristics after cycling stress are obtained by buried charge cell structure. Moreover, Vth shift by interference between adjacent cells has smaller dependence on the cell-cell space than Vth window improvement when the half pitch is constant. These results show that the buried charge planar MONOS cell is suitable for Flash memory with 20nm-node and beyond.

Anomalous diffusion of dopant in Si substrate during oxynitride process

Unexpectedly enormously enhanced diffusions of B and P in Si substrate during gate oxynitride process have been clarified for the first time. The apparent diffusion enhancement is observed in the reoxidation process after nitridation in NH/sub 3/ ambient. The oxidation enhanced diffusion (OED) factors of B and P are about 15 times larger than the normal OED factor, which is ascribed to the increase of interstitial Si at oxynitride/Si interface. The enormously enhanced diffusion affects the device characteristics and should be taken into account in order to perform accurate simulation for submicron MOSFETs with oxynitride gate.

Quick address detection of anomalous memory cells in a flash memory test structure

A novel scheme for quick address detection of anomalous memory cells having the highest and lowest threshold voltages in a flash memory test structure is described. A test structure with a large memory cell array has been developed to evaluate reliability of flash memory cells before fabrication of a new generation of flash memory devices. In this test structure, each terminal branch of a tree-structured column selector is connected to each bitline of the array. And a simple threshold voltage distribution monitor circuit (VTDM) which we have already proposed is connected to the other end of the bitlines. A proposed Multi-Address Scanning Scheme (MASS) is performed by the tree-structured column selector with monitoring the output of VTDM. The detection time has been reduced to 1.12% in the case of 2048 columns. This novel scheme is suitable for performing reliability tests, such as program/erase endurance test and data retention test.