Yasuko Yoshida

Failure analysis of 6T SRAM on low-voltage and high-frequency operation

Careful analysis of SRAM bit failure at high-frequency operation has been described. Using the nanoprober technique, MOS characteristics of failure bit in actual memory cells had been measured directly. It was confirmed that the drain current of a PMOS was about one order in magnitude smaller and the threshold voltage was about 1 V higher than that for normal bits. A newly developed, unique selective etching technique using hydrazine mixture showed these degradations were caused by local gate depletion, and TEM observation showed the PMOS gate poly-Si of the failure bit had a huge grain. Minimizing grain size of the gate poly-Si is found to be quite effective for improving drain current degradation and suppressing this failure mode.

A stacked split word-line (SSW) cell for low-voltage operation, large capacity, high speed SRAMs

Stacked Split Word-Line cell technology suitable for low voltage operation, large capacity and high speed SRAMs has been proposed. Two pull-down transistors and two access transistors are fabricated employing two separate gate formations. A pair of split word-lines is stacked over pull-down transistors. That permits large cell ratio in small cell area and independent optimization of pull-down and access transistors. Threshold voltage of access transistors is lowered to improve cell stability. Top gate thin film polysilicon transistor and Vcc plate are used to make cell node capacitor and improve soft error immunity. This technology is applied to a fast 16M bit SRAM and enabled a 7.16 /spl mu/m/sup 2/ cell area in relaxed 0.4 /spl mu/m layout rule utilizing conventional i-line stepper without phase-shift masks.<<ETX>>

Analysis of SRAM bit failure at high frequency operation

Careful analysis on SRAM bit failure at high frequency operation has been described. Using nano-prober technique, MOS characteristics of failure bit in actual memory cell had been measured directly. That confirmed drain current of PMOS was about one order smaller and threshold voltage was about 1 V higher than that of normal bit. Newly developed unique selective etching technique using hydrazine mixture showed these degradations ware caused by local gate depletion. And TEM observation showed PMOS gate poly-Si of failure bit had a huge grain. Minimizing grain size of gate poly-Si is found to be quite effective for improving drain current degradation and suppressing failure mode.

A highly manufacturable 0.18 /spl mu/m generation logic technology

A 0.18 /spl mu/m generation logic technology has been developed with 0.14 /spl mu/m gate length transistors. Guidelines to suppress mechanical stress in shallow trench isolation are clearly described. Stable Co salicide process has been integrated with the combination of NO treated gate oxide and BF/sub 2/ source drain ion implantation. Amorphous Si with RTA is the key to control grain size and suppress large variation of drain current in small size transistors. Two kinds of metallization systems, aluminum with SiOF dielectrics and dual damascene Cu are developed in the same layout rule.

Threshold voltage-related soft error degradation in a TFT SRAM cell

This is the first report of abnormal behavior in the soft error rate (SER) dependence on supply voltage (Vcc) for a bottom-gated polysilicon PMOS thin-film transistor (TFT) static random access memory (SRAM). We found that the TFT SER does not continuously improve (as is expected and desirable) with increasing Vcc when Vcc exceeds -Vth (threshold voltage) of the TFT within a range of about 0-2 V. This was confirmed with samples of TFT with Vth intentionally varied from 0 to -5 V (by adjusting channel doping). A possible explanation of this Vcc independence is proposed in the form of a SPICE simulation with as little as a 0.1-V TFT transient Vth shift due to the TFTs floating body. The accelerated SER was measured by using an Americium alpha particle source.