Toshiaki Yamanaka

A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logic

A 3.8-ns, 257-mW, 16*16-b CMOS multiplier with a supply voltage of 4 V is described. A complementary pass-transistor logic (CPL) is proposed and applied to almost the entire critical path. The CPL consists of complementary inputs/outputs, an nMOS pass-transistor logic network, and CMOS output inverters. The CPL is twice as fast as conventional CMOS due to lower input capacitance and high logic functionality. Its multiplication time is the fastest ever reported, even for bipolar and GaAs ICs, and it can be enhanced further to 2.6 ns with 60 mW at 77 K. >

A 1.5-ns 32-b CMOS ALU in double pass-transistor logic

Describes circuit techniques for fabricating a high-speed adder using pass-transistor logic. Double pass-transistor logic (DPL) is shown to improve circuit performance at reduced supply voltage. Its symmetrical arrangement and double-transmission characteristics improve the gate speed without increasing the input capacitance. A carry propagation circuit technique called conditional carry selection (CCS) is shown to resolve the problem of series-connected pass transistors in the carry propagation path. By combining these techniques, the addition time of a 32-b ALU can be reduced by 30% from that of an ordinary CMOS ALU. A 32-b ALU test chip is fabricated in 0.25- mu m CMOS technology using these circuit techniques and is capable of an addition time of 1.5 ns at a supply voltage of 2.5 V. >

A 4.4 ns CMOS 54/spl times/54-b multiplier using pass-transistor multiplexer

A 54/spl times/54-b multiplier using pass-transistor multiplexers has been fabricated by 0.25 /spl mu/m CMOS technology. To enhance the speed performance, a new 4-2 compressor and a carry lookahead adder (CLA), both featuring pass-transistor multiplexers, have been developed. The new circuits have a speed advantage over conventional CMOS circuits because the number of critical-path gate stages is minimized due to the high logic functionality of pass-transistor multiplexers. The active size of the 54/spl times/54-b multiplier is 3.77/spl times/3.41 mm. The multiplication time is 4.4 ns at a 3.5-V power supply. >

Advanced TFT SRAM cell technology using a phase-shift lithography

An advanced TFT memory cell technology has been developed for making high-density and high-speed SRAM cells. The cell is fabricated using a phase-shift lithography that enables patterns with spaces of less than 0.25 /spl mu/m to be made using the conventional stepper. Cell area is also reduced by using a small cell-ratio and a parallel layout for the transistor. Despite the small cell-ratio, stable operation is assured by using advanced polysilicon PMOS TFTs for load devices. The effect of the Si/sub 3/N/sub 4/ multilayer gate insulator on the on-current and the influence of the channel implantation are also investigated. To obtain stable operation and extremely low stand-by power dissipation, a self-aligned offset structure for the polysilicon PMOS TFT is proposed and demonstrated. A leakage current of only 2 fA/cell and an on-/off-current ratio of 4.6/spl times/10/sup 6/ are achieved with this polysilicon PMOS TFT in a memory cell, which is demonstrated in a experimental 1-Mbit CMOS SRAM chip that has an access time of only 7 ns. >

A 3.8 ns CMOS 16atimes;16 multiplier using complementary pass transistor logic

A 3.8-ns, 257-mW CMOS 16×16 multiplier with a supply voltage of 4 V is described. A complementary pass transistor logic (CPL) is proposed and applied to almost the entire critical path. The CPL consists of complementary input/output, an NMOS-pass-transistor logic network, and CMOS output inverters. The CPL is twice as fast as the conventional CMOS due to lower input capacitance and greater logic construction ability. Its multiplication time is believed to be the fastest ever reported, even including times of bipolar and GaAs ICs, and it is shown to be further enhanced to 2.6 ns and 60 mW at 77 K

0.1 mu m CMOS devices using low-impurity-channel transistors (LICT)

Summary form only given. It was found that LICTs are very effective for providing low threshold voltages with good turn-offs in 0.1 mu m CMOS devices. Attention is given to device fabrication criteria, key process technologies used, and the features achieved using LICTs.<<ETX>>

A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers

A 4-Mb CMOS SRAM with 3.84 /spl mu/m/sup 2/ TFT load cells is fabricated using 0.25-/spl mu/m CMOS technology and achieves an address access time of 6 ns at a supply voltage of 2.7 V. The use of a current sense amplifier that is insensitive to its offset voltage enables the fast access time. A boosted cell array architecture allows low voltage operation of fast SRAMs using TFT load cells. >

A 7-ns 140-mW 1-Mb CMOS SRAM with current sense amplifier

A 7-ns 140-mW 1-Mb CMOS SRAM was developed to provide fast access and low power dissipation by using high-speed circuits for a 3-V power supply: a current-sense amplifier and pre-output buffer. The current-sense amplifier shows three times the gain of a conventional voltage-sense amplifier and saves 60% of power dissipation while maintaining a very short sensing delay. The pre-output buffer reduces output delays by 0.5 ns to 0.75 ns. The 6.6- mu m/sup 2/ high-density memory cell uses a parallel transistor layout and phase-shifting photolithography. The critical charge that brings about soft error in a memory cell can be drastically increased by adjusting the resistances of poly-PMOS gate electrodes. This can be done without increasing process complexity or memory cell area. The 1-Mb SRAM was fabricated using 0.3- mu m CMOS quadrupole-poly and double-metal technology. The chip measures 3.96 mm*7.4 mm (29 mm/sup 2/). >

A polysilicon transistor technology for large capacity SRAMs

A polysilicon PMOS cell technology is discussed. Bottom-gated polysilicon PMOS transistors are stacked over NMOS transistors, and a 17 mu m/sup 2/ cell size is realized with a 0.6 mu m design rule. In order to achieve high-performance polysilicon PMOS, both gate oxide and channel polysilicon thicknesses of the PMOS are reduced to 40 nm. A 0.4 mu m length gate-to-drain offset structure is adopted. Moreover, two novel approaches to O/sub 2/ plasma treatment prior to metal H/sub 2/-N/sub 2/ anneal and oxidation of channel polysilicon have been found to be effective for achieving excellent polysilicon PMOS characteristics. As a result, polysilicon PMOS which has a 25 fA off-current (V/sub d/=-5 V, V/sub g/=0 V) and a 0.1 nA on-current (V/sub d/=-5 V, V/sub g/=-2 V) has been realized.<<ETX>>

A 25 mu m/sup 2/, new poly-Si PMOS load (PPL) SRAM cell having excellent soft error immunity

A 25- mu m/sup 2/ poly-Si PMOS load SRAM (static random access memory) cell, called a PPL cell, has been developed. The cell has been excellent retention characteristics, high soft-error immunity, and low standby power. These advantages are achieved using poly-Si PMOS loads and cross-coupled stacked capacitors formed between the NMOS and the stacked poly-Si PMOS. A large poly-Si PMOS ON current lowers retention voltage to less than 0.5 V and the soft error rate (SER) under high-speed operation by about an order of magnitude. A 5-fF cross-coupled capacitor improves the retention mode SER by more than an order of magnitude and low standby power is attained with a 0.1-pA OFF current of the poly-Si PMOS. The performance has been evaluated using a 4-kbit SRAM. The cell area has been reduced to 25.38 mu m/sup 2/ using half-micron CMOS technology.<<ETX>>