Yasuo Ikawa

A 1K-gate GaAs gate array

A 1050-gate GaAs gate array connected as a 6 × 6b parallel multiplier, which exhibits a multiplication time of 10.6ns and 350mW power dissipation, will be covered.

A technology roadmap of assistive technologies for dementia care in Japan.

The number of elderly people in Japan is growing, which raises the issue of dementia, as the probability of becoming cognitively impaired increases with age. There is an increasing need for caregivers, who are well-trained, experienced and can pay special attention to the needs of people with dementia. Technology can play an important role in helping such people and their caregivers. A lack of mutual understanding between caregivers and researchers regarding the appropriate uses of assistive technologies is another problem. A vision of person-centred care based on the use of information and communication technology to maintain residents’ autonomy and continuity in their lives is presented. Based on this vision, a roadmap and a list of challenges to realizing assistive technologies have been developed. The roadmap facilitates mutual understanding between caregivers and researchers, resulting in appropriate technologies to enhance the quality of life of people with dementia.

A 2K-gate GaAs gate array with a WN gate self-alignment FET process

A 2K-gate DCFL GaAs gate array has been successfully fabricated with a WN gate self-alignment GaAs MESFET process. Chip size was 4.59 mm/spl times/4.73 mm. A basic cell, consisting of one DFET and three EFETs, can be programmed as an inverter or a two or three-INPUT NOR gate by personalizing with first- and second-level interconnection and via hole masks. The I/O buffer was implemented with a large DCFL push-pull circuit. The unloaded propagation delay time was 42 ps/gate at a power dissipation of 0.5 mW/gate. The increases in delay time due to various loading capacitance were 11-ps/fan-in. 16-ps/fan-out, 59-ps/1-mm interconnection and 0.95 ps/crossover (area: 2 /spl mu/m/spl times/3 /spl mu/m). An 8/spl times/8-bit parallel multiplier was fabricated on this gate-array chip. A multiplication time of 8.5 ns was achieved at a power dissipation of about 400 mW including I/O buffers.

A 42ps 2K-gate GaAs gate array

TO INCREASE speed of microelectronic systems, it is the interchip signal delay that should be reduced by maximizing the integration level. As the integration level increases, however, the development time becomes longer. The rapid development of LSIs is increasingly important because the product life cycle has been becoming shorter. A gate array approach is effective under these circumstances. Very high-speed ICs such as Si bipolar ECL logic, is no exception, and 2.5-5.0K gate gate arrays with 0.35-0.5011s loaded gate delay have been developed. However, very large power consumption, 5-8W/chip, limit their field of application. GaAs gate arrays have attracted interest as a replacement for the Si ECL gate array because of the smaller gate delay and lower power consumption. To date, several types of GaAs gate array have been reported’ ’2’3. This paper will describe a 2K-gate DCFL (Direct Coupled FET Logic) GaAs gate array with a 42ps unloaded and 215ps loaded gate delay at a power dissipation of 0.5mW/gate. An 8 x 8 b parallel multiplier has been fabricated on this chip. A multipiication time of 8.5ns was achieved at a power dissipation of 400mW, an improvement over an 8 x 8b Si ECL multiplier with custom design . The current design also consumes about 35Yo less power.

Dynamic service framework approach to sustainable service value shift applied to traditional Japanese tea ceremony

In order to plan new services, one needs to understand not only the related technologies and products, but also the value sense and concepts of individual and institutional customers, their behavioral patterns, as well as the background social system. Especially with hospitality, entertainment and art services, the historical background, hospitality culture and regional traditions often sustain and enhance the value of service for the customer. This paper applies a modern dynamic multidisciplinary framework to study the historical shift and present sustainability of traditional services. The framework facilitates the analysis of service value and service shift trends by placing and tracing individual services in a service domain space according to two major axes: classification in a ldquoneeds levelrdquo-ldquoservice using placerdquo hierarchy proposed earlier by the author, and the degree of customer participation. The dynamic framework is applied, in the context of recent achievements of structural anthropology, to the historical shift around the 16th century of Japanese traditional tea ceremony, attempting to gain insight applicable to the sustainable innovation of modern hospitality, entertainment and art services.

Modeling of high-speed, large-signal transistor switching transients from s-parameter measurements

A new technique has been developed to derive the large-signal transient response of semiconductor devices from small-signal frequency response data. The large-signal switching response can be calculated for an arbitrary input signal voltage and rise time. This new technique utilizes the Fourier transformation to combine arrays of small-signal data to compute the response waveform. The input waveform is decomposed into a superposition of small pulses. The response to each pulse is obtained by Fourier transformation techniques, using s-parameter data at appropriate bias points. The sum of these responses approximates the overall transient response. Simulations were performed for a GaAs MESFET for step inputs with the rise times of 8 ns and 150 ps. Good agreement was obtained between simulated waveforms and measured output waveforms in rise time, magnitude, and waveform shape. This algorithm is general and will work for other measured small-signal transfer parameters as functions of frequency and bias.

A one-day chip: an innovative IC construction approach using electrically reconfigurable logic VLSI with on-chip programmable interconnections

A new custom IC design methodology and the associated logic VLSI chip, which offer an ultimately fast turnaround-time logic IC construction method, are proposed. The chip contains various kinds of logic functional blocks, such as inverters, NORs, NANDs, flip-flops, shift registers, counters, adders, multiplexers, and ALUs. Up to 200 SSI/MSI standard logic blocks can be provided. The E/SUP 2/PROM-type MOSFET switch matrix is adjacent to the functional blocks, in order to connect any output to specific inputs of the functional blocks. It also offers a ready-to-test aid, obtained by monitoring the signal waveform developed inside the chip. These features have the advantage over the present custom IC design methods (gate array, standard cell, silicon compiler, programmable logic array) that the designer can easily redesign the logic to obtain a digital system in an IC in a single day.

Minority Carrier Diffusion Length in Si Ribbon Solar Cells

Minority carrier diffusion length Lp in Si ribbon solar cells was investigated using a scanning electron microscope. It was found that Lp was lowered at irregular crystal boundaries. The low Lp region around an irregular boundary was only 10~20 µm in width, and occupied less than 5 percent of the total solar cell area in most cases. The value of Lp in regions without crystal boundaries scattered appreciably. Average Lp value had no dependence on carrier density whose range was 1016~1017 cm-3, which means that photocurrent is almost independent of carrier density. As a result, it is expected that ribbon crystals with higher carrier densities are preferable as base material for solar cells to obtain higher efficiency.

Multidisciplinary framework-based service modeling applied to service coursework and business planner interaction

Launching new high-value-added services calls for systematic methodologies based on multidisciplinary framework enabling the transformation from service concept to real service. The collaboration of business planers from various kinds of service and the sharing and assignment among individuals/organization, goods/infrastructure, technology/system require the establishment of a common framework and service modeling approaches based on multidisciplinary studies. The present paper applies the service modeling approach proposed by the authors to service coursework for undergraduate, graduate and post-graduate carrier-track students from some universities. The analysis of planning process and results demonstrate the potential for application to various service areas. The authors interviewed key service planner in real IT service businesses, with a focus on the service modeling processes and its results. The interviews confirmed the potential for application to actual service planning, and provided leads for refining the service modeling approach.

Analysis of Japanese MOT education requirements by a Needs-Seeds matrix

In recent years, MOT (management of technology) has been a hot issue in Japan for surviving severe competition in science and technology research, development and business. In this paper, a tendency of newly developed MOT programs through national project until the end of 2003 is analyzed. This analysis just covers limited number of developed programs that are available to be referred at the time of writing this paper through open source, but still might be useful to consider a direction of future development by showing Needs-Seeds matrix that was constructed with current seeds (elements of developed programs) and potential needs (social and commercial requirements). It is suggested that this type of analysis is useful and should be conducted on a regular basis to make continuous improvement of MOT programs.