A. Kameyama

An 8-bit slice GaAs bus logic LSI for a high-speed parallel processing system

An 8-b slice GaAs bus logic LSI (BL) has been developed for a high-speed interconnection network in a multiple-instruction multiple-data stream (MIMD) parallel processing system. The BL has been designed using a novel standard-cell approach called the building-cell methodology, which leads to a high integrated density of 25000 devices in a 7*7-mm/sup 2/ chip. The BL consists of 3376 logic gates and a 76-b dual-port register file (RF), which has as a new function a multi-address read/write operation for efficient data transfer. The BL was fabricated by a 0.8- mu m WN/sub x/ gate LDD (lightly doped drain) MESFET process, and fully functionally tested with an average yield of 20%. A 10-ns cycle time operation was achieved with a power dissipation of 5.5 W. This result reveals that a network with 256 GaAs BLs and 64 processor units can realize a maximum data transfer rate of 2.56 Gbyte/s. >

A lightly doped deep drain GaAs MESFET structure for linear amplifiers of personal handy-phone systems

An improved GaAs MESFET structure, named a buried p-layer lightly doped deep drain (BP-LD3) structure, is proposed. This structure can be fabricated by the conventional self-aligned gate and selective ion implantation technologies, and the FET characteristics show a high transconductance, a high breakdown voltage, and a low drain-source resistance. The lightly doped deep drain characterizing this structure was introduced on the basis of a two-dimensional numerical analysis including an impact ionization for a buried p-layer lightly doped drain (BP-LDD) structure which has been applied for high-speed digital ICs. The simulated results clarified that a low breakdown voltage of the BP-LDD structure originates from a high rate of carrier generation due to the impact ionization in the lightly doped drain region. The reason is that both electric field and current density become high in the region. In the new BP-LD3 structure, the electron current expands due to the deep formation of lightly doped drain, therefore impact ionization is reduced. This BP-LD3 structure was fabricated and the FET characteristics were compared with those of the conventional BP-LDD structure, and a structure which is now being studied for linear amplifiers of 1.9 GHz personal handy-phone systems. The measured breakdown voltage of 8.1 V, transconductance of 360 mS/mm, and drain-source resistance of 2.5 /spl Omega//mm for the BP-LD3 structure indicate high potentiality for analog applications.

A WN x gate self-aligned GaAs p-channel MESFET for complementary logic

The Schottky barrier of reactively sputtered WNxto p-type GaAs has been investigated. Postdeposition heat treatments above 500°C led to a reduction in the barrier height but for lamp annealing at 740°C the barrier heights are 0.68 eV. Self-aligned p-channel MESFETs were fabricated with WNxgates by a refractory metal process involving the above heat treatment. The Schottky-barrier heights were close to the expected values. K-values of FETs with 2 µm × 24 µm gates were 0.088 mA/V2, consistent with previously reported results. SPICE simulation studies carried out for a variety of complementary-type logic gates, indicate that power dissipation × delay time products of less than 10 fJ may be achievable over the power range 5-50 µW/gate. Thus complementary logic may be useful for applications where low power dissipation is at a premium.

GaAs high-speed data transfer network for a parallel processing system

A GaAs high-speed data transfer network connecting multiple processor units (PUs) has been successfully developed in a module with 8-b slice GaAs bus logic (BL) LSIs, which fully functioned at more than 100 MHz. The GaAs multichip module consists of 12 GaAs BL LSIs in a 3*4 matrix. In the parallel processing system, a 4 Gbit/s data transfer data (32 b*120 MHz) can be realized by four stacked modules of 48 GaAs BLs.<<ETX>>

A 2 Gb/s GaAs 128-bit shift register using standard cells with 0.5 mu m WN/sub x/ gate MESFETs

A 2-Gb/s GaAs 128-bit shift register was designed using standard cells, and was successfully fabricated using an advanced 0.5- mu m WN/sub x/-gate self-alignment MESFET process with a Mg-implanted p-layer under the n-channel. The chip size was 5.05 mm*3.65 mm, in which about 1050 gates were integrated. The yield of fully functional chips over a 3-in. wafer was as high as 20-30%. The chips operated at 2.0-GHz clock frequency with 3.4-W power dissipation.<<ETX>>