Katsue Kawakyu

A novel resonant-type GaAs SPDT switch IC with low distortion characteristics for 1.9 GHz personal handy-phone system

A GaAs SPDT switch IC operating at a low power supply voltage of 2.7 V has been developed for use in Personal Handy-Phone System in the 1.9 GHz band. In combination with MESFETs with low on-resistance and high breakdown voltage, the resonant-type switch IC utilizes stacked FETs and an additional shunt capacitor at the receiver side in order to realize low insertion loss, high isolation and low distortion characteristics. An insertion loss of 0.55 dB and an isolation of 35.8 dB were obtained at 1.9 GHz. The IC also achieved a second order distortion of -54.3 dBc and an adjacent channel leakage power of -66 dBc at 600 kHz apart from 1.9 GHz at 19 dBm output power.

High-efficiency monolithic GaAs power MESFET amplifier operating with a single low voltage supply for 1.9-GHz digital mobile communication applications

A monolithic GaAs power amplifier IC using refractory WN/sub xW self-aligned gate power MESFETs has been developed for 1.9-GHz digital mobile communication systems, such as the Japanese personal handy phone system. The power amplifier operates with high efficiency and low distortion with a single low voltage supply of 2.7-3.0 V, by virtue of small drain knee voltage, high transconductance and sufficient breakdown voltage of the power MESFET. An output power of 23.7 dBm and a high power-added efficiency of 24.2% were attained at 3 V for 1.9-GHz /spl pi4-shifted QPSK (quadrature phase shift keying) modulated input when adjacent channel leakage power was -58 dBc at 600 kHz apart.<<ETX>>

High efficiency, low adjacent channel leakage 2-V operation GaAs power MESFET amplifier for 1.9-GHz digital cordless phone system

A low-voltage GaAs power amplifier for 1.9-GHz digital mobile communication applications such as PHS handsets has been developed, using refractory WNx/W self-aligned gate MESFETs with p-pocket layers. This power amplifier operates with a single low 2-V supply, and an output power of 21.0 dBm, a power gain of 22.3 dB, a low dissipated current of 162.9 mA and a high power-added efficiency of 38.5% were attained with a low 600-kHz adjacent channel leakage power of -58.0 dBc for 1.9-GHz /spl pi//4-shifted QPSK modulated input.

A 2-V operation RF front-end GaAs MMIC for PHS hand-set

A single 2-V operation RF front-end MMIC has been developed using three kinds of self-aligned gate MESFETs. Its transmitter block of a power amplifier with an antenna switch exhibited a power gain of 28.9 dB and a high power-added efficiency of 27.0% at 20.5-dBm output power. The receiver block of a low-noise amplifier with the antenna switch exhibits a noise figure of 3.4 dB and a gain of 11.1 dB.A single 2-V operation RF front-end MMIC has been developed using three kinds of self-aligned gate MESFETs. Its transmitter block of a power amplifier with an antenna switch exhibited a power gain of 28.9 dB and a high power-added efficiency of 27.0% at 20.5-dBm output power. The receiver block of a low-noise amplifier with the antenna switch exhibits a noise figure of 3.4 dB and a gain of 11.1 dB.

An 8-bit slice GaAs bus logic LSI for a high-speed parallel processing system

An 8-b slice GaAs bus logic LSI (BL) has been developed for a high-speed interconnection network in a multiple-instruction multiple-data stream (MIMD) parallel processing system. The BL has been designed using a novel standard-cell approach called the building-cell methodology, which leads to a high integrated density of 25000 devices in a 7*7-mm/sup 2/ chip. The BL consists of 3376 logic gates and a 76-b dual-port register file (RF), which has as a new function a multi-address read/write operation for efficient data transfer. The BL was fabricated by a 0.8- mu m WN/sub x/ gate LDD (lightly doped drain) MESFET process, and fully functionally tested with an average yield of 20%. A 10-ns cycle time operation was achieved with a power dissipation of 5.5 W. This result reveals that a network with 256 GaAs BLs and 64 processor units can realize a maximum data transfer rate of 2.56 Gbyte/s. >

A 6 K-gate GaAs gate array with a new large-noise-margin SLCF circuit

A 6 K-gate GaAs gate array has been successfully designed and fabricated using a novel large-noise-margin Schottky-diode level-shifter capacitor-coupled FET logic (SLCF) circuitry and a WN/SUB x/ gate selfaligned lightly doped drain (LDD) structure GaAs MESFET process. Chip size was 8.0/spl times/8.0 mm/SUP 2/. A basic cell can be programmed as an SLCF inverter, a two-input NOR, or a two-input NAND gate. The unloaded propagation delay time was 76 ps/gate a 1.2-mW/gate power dissipation. The increases in delay time due to various loading capacitances were 10 ps/fan-in, 45 ps/fan-out, and 0.64 ps/IF. A 16-b serial-to-parallel-to-serial (S/P/S) data-conversion circuit was constructed on the gate array as an application example. A maximum operation frequency of 852 MHz was achieved at a 952-mW power dissipation, including I/O buffers.

Single low voltage supply operation GaAs power MESFET amplifier with low-distortion gain-variable attenuator for 1.9-GHz personal handy phone systems

A GaAs power amplifier with a low-distortion, 10-dB gain attenuator has been developed for 1.9-GHz personal handy phone system (PHS). Single low 2.4-V supply operation was achieved by using power MESFETs with p-pocket layers. Furthermore, on account of an attenuator with cascaded shunt FET structure, very low 600-kHz adjacent channel leakage power (ACP) with sufficient, constant output power was attained regardless of any controlled gain. An output power of 21.1 dBm, a low dissipated current of 157 mA and a high power-added efficiency of 37.2% were obtained with ACP of -55 dBc.

Cell-shifting compaction of building-cell methodology for high-speed GaAs standard-cell LSIs

The authors propose a novel cell-shifting compaction concept for building-cell methodology to realize high-speed GaAs standard-cell LSIs. This compaction reduces the layout-area and stray capacitance and the inductance of routings, and leads to a large degree of freedom for cell placement. The cell-shifting compaction is also a valid approach for Si standard-cell LSIs.<<ETX>>

A 2 Gb/s GaAs 128-bit shift register using standard cells with 0.5 mu m WN/sub x/ gate MESFETs

A 2-Gb/s GaAs 128-bit shift register was designed using standard cells, and was successfully fabricated using an advanced 0.5- mu m WN/sub x/-gate self-alignment MESFET process with a Mg-implanted p-layer under the n-channel. The chip size was 5.05 mm*3.65 mm, in which about 1050 gates were integrated. The yield of fully functional chips over a 3-in. wafer was as high as 20-30%. The chips operated at 2.0-GHz clock frequency with 3.4-W power dissipation.<<ETX>>