Atsufumi Shibayama

Fast optical channel recovery in field demonstration of 100-Gbit/s Ethernet over OTN using real-time DSP

A field trial of 100-Gbit/s Ethernet over an optical transport network (OTN) is conducted using a real-time digital coherent signal processor. Error free operation with the Q-margin of 3.2 dB is confirmed at a 100 Gbit/s Ethernet analyzer by concatenating a low-density parity-check code with a OTN framer forward error correction, after 80-ch WDM transmission through 6 spans x 70 km of dispersion shifted fiber without inline-dispersion compensation. Also, the recovery time of 12 msec is observed in an optical route switching experiment, which is achieved through fast chromatic dispersion estimation functionality.

A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power motion estimation and clocking

A 1.5-W single-chip MPEG-2 MP@ML real-time video encoder large scale integrated circuit (LSI) has been developed. To form an MPEG-2 encoder system, we employ two 16-Mb synchronous DRAMs, a microprocessor unit (MPU), and an audio encoder LSI. Owing to a two-step hierarchical search scheme and a novel adaptive search window scheme, the search range of motion estimation is -48/+47 horizontal and -96/+15.5 vertical, and the pseudo search range, which is the size when the location of the search window is adaptively shifted, is -96/+95 horizontal and -32/+31.5 vertical. We have also developed low-power clocking techniques, i.e., demand-clock controller, local-clock controller, and low-power flip-flops, which can eliminate waste of power in clocking. We have successfully fabricated these new designs as a low-power single-chip MPEG-2 encoder LSI. The operating frequency except for a synchronous DRAM interface unit and a video in/out unit is 54 MHz. The supply voltage to the first and second search engines in a motion estimation unit can be successfully lowered to 2.5 V and the others are 3.3 V. Into a 12.45/spl times/12.45 mm/sup 2/ chip with 0.35-/spl mu/m CMOS and triple-metal layer technology are integrated 3.1 M transistors.

An autonomous reconfigurable cell array for fault-tolerant LSIs

The integration density achieved by the sub-0.l/spl mu/m ULSI causes a serious reliability problem. Redundancy is essentially the solution to the problem, but it is difficult to introduce redundancy to logic LSIs because of their functional complexity compared to memory LSIs. To overcome this difficulty, the autonomous reconfigurable cell array (ARCA) takes advantage ofthe redundancy, regularity, and programmability of reconfigurable logic circuits. It self-detects faults in real-time and automatically recovers while remaining on-line. Fault-tolerant LSIs can be obtained simply by mapping an objective circuit onto an ARCA in the same way as in conventional programmable LSIs.

Deterministic inter-core synchronization with periodically all-in-phase clocking for low-power multi-core SoCs

Periodically all-in-phase clocking (8-step frequency increments with a 4.5 ns switching time) and deterministic synchronous bus wrappers (synchronized data transfer among different frequency cores) are developed for dynamic voltage- and frequency-scaling multi-core SoCs. A maximum of 60% power reduction in MPEG-4 decoding with 1.5 to 2/spl times/ throughput increase are confirmed.

Skew-Tolerant Global Synchronization Based on Periodically All-in-Phase Clocking for Multi-Core SOC Platforms

A periodically all-in-phase clock generator and a skew-tolerant bus wrapper have been developed for multi-core SOC platforms. The clock generator produces clock frequencies in 81-steps, and the bus wrapper makes possible deterministic data transfer among different frequency clocks even when inter-clock skew is as high as 2 clock cycle times. A combination of the clock generator, the bus wrapper, and loosely balanced global clock distribution serves to ease chip-timing design while maintaining deterministic chip behavior.

Device-deviation tolerant over-1 GHz clock distribution scheme with skew-immune race-free impulse latch circuits

Clock skew (and jitter) is becoming the major obstacle to high-frequency clock distribution in sub-quarter micron CMOS LSIs, because skew cannot be scaled down even by use of scaled devices and may significantly increase as a result of device and operating environment deviations. To overcome this obstacle, the authors present skew-immune race-free impulse latch circuits and a reduced-skew ring-type clocking scheme. The 1 GHz clock test chip is integrated into a 6/spl times/6 mm/sup 2/ die with 0.18 /spl mu/m CMOS and double-layer-metal technology. The supply voltage is 1.8 V. The threshold voltage of the nMOS transistors is about 0.3 V and that of the pMOS transistors is about -0.3 V. 1 GHz global clock distribution shows less than 50 ps clock skew for those points on the chip.