Yasuyuki Tamura

Novel multi-bit SONOS type flash memory using a high-k charge trapping layer

We demonstrated SONOS flash memory with a SiO/sub 2//High-k/SiO/sub 2/ structure based on a 2-bit/cell scheme. We evaluated three kinds of high-k dielectric films which were Si/sub 3/N/sub 4/, Al/sub 2/O/sub 3/ and HfO/sub 2/. Among these films, Al/sub 2/O/sub 3/ showed superior retention characteristics. The charge loss amount of Al/sub 2/O/sub 3/ at 150/spl deg/C is almost the same as that of Si/sub 3/N/sub 4/ at 25/spl deg/C. HfO/sub 2/ showed poor retention characteristics. In addition, we have found that each film has a different charge loss mechanism. We speculate that Si/sub 3/N/sub 4/ causes vertical charge migration, Al/sub 2/O/sub 3/ causes scarcely any leakage, and HfO/sub 2/ causes lateral charge migration. As a consequence, Al/sub 2/O/sub 3/ is very suitable for a charge trapping layer in multi-bit SONOS memory.

SiN-capped HfSiON gate stacks with improved bias temperature instabilities for 65 nm-node low-standby-power transistors

This paper describes the SiN-capped HfSiON gate stacks for 65 nm-node low-standby-power transistors with improved bias temperature instabilities (BTI). By employing SiN-cap on HfSiON and the counter-implant for adjustment of pFETs threshold voltage (V/sub TH/), the symmetrical V/sub TH/ values for nFETs and pFETs have been obtained. The nitrogen incorporation in the interfacial oxide prevents the interface states generation under positive bias temperature stress. Negative BTI can be improved by reducing the thickness of SiN-cap. 10-year lifetimes for both positive and negative BTI have been achieved.

Dielectric breakdown mechanism of HfSiON/SiO/sub 2/ gate dielectric

The breakdown mechanism of HfSiON/SiO/sub 2/ gate stacks is discussed, based on studies of the band diagram, carrier separation and charge pumping measurements. We found that both holes and electrons contribute to BD and therefore the combination of the stress polarity and the device type should be chosen carefully to evaluate the reliability.

High performance and highly reliable deep submicron CMOSFETs using nitrided-oxide

High performance and highly reliable CMOSFETs have been obtained using newly-developed nitrided-oxide processing, which features the localization of the nitrogen profile at the SiO/sub 2/-Si interface, and giving different nitrogen concentrations between the gate and LDD area. In p-MOSFETs, I/sub on/ can be increased by 12%, and I/sub off/ can be decreased by 50% compared with pure oxide. Also, in n-MOSFETs, hot carrier reliability significantly improves.

Importance of Leakage Current Noise Analysis for Accurate Lifetime Prediction of High-k Gate Dielectrics

for Accurate Lifetime Prediction of High-k Gate Dielectrics Kenji OKADA, Hiroyuki OTA , Tsuyoshi HORIKAWA , Yasuyuki TAMURA 3 Takaoki SASAKI , Tomonori AOYAMA , Fumio OOTSUKA , and Akira TORIUMI 1,2 MIRAI-ASET, AIST Tsukuba SCR Building, 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan. Phone: +81-29-849-1549, Fax: +81-29-849-1529, E-mail: okada.kenji@mirai.aist.go.jp 1 MIRAI-ASRC, AIST Tsukuba, Japan, 2 Department of Materials Science, The University of Tokyo, Japan, 3 Semiconductor Leading Edge Technologies (Selete), AIST Tsukuba, 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan.

Impact of Nitrogen Profile in Gate Oxynitride on Complementary Metal Oxide Semiconductor Characteristics

We demonstrated that the control of the nitrogen profile in the gate oxynitride for complementary metal oxide semiconductors (CMOSs) is very important. We grew NO or N2O nitrided gate oxide at 800°C or 900°C to prepare three kinds of oxynitrides with different nitrogen profiles, and investigated the atomic configuration and the chemical state of nitrogen using secondary ion mass spectroscopy and X-ray photoelectron spectroscopy. Furthermore, we fabricated CMOS field effect transistors with gate oxide and oxynitride, and evaluated the interface state density and the hot carrier immunity. By systematical investigation of the relationship between the nitrogen profile and the electrical characteristics, we found that the nitrogen in the oxynitride should exist only at the interface for realizing the CMOS devices having high performance and high reliability.

Effect of in-situ nitrogen doping into MOCVD-grown Al/sub 2/O/sub 3/ to improve electrical characteristics of MOSFETs with polysilicon gate

The effect of nitrogen doping into Al/sub 2/O/sub 3/ gate dielectric grown by Metal Organic Chemical Vapor Deposition (MOCVD) on MOS device characteristics is described for the first time. The nitrogen doped Al/sub 2/O/sub 3/ (Al/sub 2/O/sub 3/:N) MOSFET has an interface trap density (D/sub it/) as low as 4.3/spl times/10/sup 10/ cm/sup -2/ eV/sup -1/, half that of non-doped Al/sub 2/O/sub 3/ (1.0/spl times/10/sup 11/ cm/sup -2/ eV/sup -1/), and has less C-V hysteresis (39 mV) than that (69 mV) of Al/sub 2/O/sub 3/. These improvements are attributed to nitrogen doping into Al/sub 2/O/sub 3/, which also improves the corresponding MOSFET characteristics of current drivability (I/sub dsat/).

Tight Distribution of Dielectric Characteristics of HfSiON in Metal Gate Devices

Leakage current characteristics with significantly reduced dispersion were achieved for HfSiON gate dielectric film by selecting TiN gate electrode with low reactivity, compared to the conventional poly-Si gate. The breakdown lifetime and its characteristic homogeneity were also enormously improved. With intensive study on these electrical characteristics, it was concluded that the concentration of oxygen vacancy was significantly reduced, giving rise to the homogeneity improvement. Moreover, we have shown an explanation for the dielectric breakdown in terms of oxygen transport in the Hf-based dielectric film.

High quality ultra-thin (4 nm) gate oxide by UV/O/sub 3/ surface pre-treatment of native oxide

A significant improvement in ultra-thin (4 nm) gate oxide quality has been carried out using UV/O/sub 3/ pre-treatment of native oxide before thermal oxidation. UV/O/sub 3/ pre-treatment makes native oxide dense and close-packed without leaving any residue species. Ultra-thin gate oxide formed by UV/O/sub 3/ pre-treatment and O/sub 3/ oxidation has been found to have excellent behavior, low leakage current, low surface state density, and superior dielectric breakdown characteristics. UV/O/sub 3/ pre-treatment looks promising for using in ultra-thin gate oxidation necessary for 0.1 /spl mu/m ULSI fabrication.