Sang-Koo Chung

Analytical model for the surface field distribution of SOI RESURF devices

An analytical model is presented to determine the electric field distribution along the semiconductor surface of silicon-on-insulator (SOI) REduced SURface Field (RESURF) devices, which allows an approximate but explicit expression for the surface field in terms of the doping concentration, the lengths of the gate and drain field plate, the thicknesses of the gate and buried oxide, and the applied voltages. Numerical simulations support the analytical results.

Surface field distribution and breakdown voltage of RESURF LDMOSFETs

An approximate but analytical expression for the surface field distribution of RESURF LDMOSFETs is presented in terms of the device parameters and the applied drain voltage, which allows calculation of the breakdown voltage via the surface field as a function of the epitaxial layer length. Analytical results are in fair agreement with numerical simulations as well as experimental results reported.

An analytical model for breakdown voltage of surface implanted SOI RESURF LDMOS

An analytical model for the breakdown voltage of the surface implanted silicon-on-insulator (SOI) REduced SURface Field (RESURP) LDMOS is presented, which allows useful design curves of breakdown voltage in terms of the device parameters, including the substrate bias voltage. Improvement on both the breakdown voltage and the on-resistance of the device due to the surface implantation is demonstrated. Numerical simulations are shown to support the analytical results.

An analytical model for minimum drift region length of SOI RESURF diodes

An analytical model for calculating the minimum drift region length of SOI RESURF diodes is presented with an expression for the maximum breakdown voltage of the device. The minimum drift region length is determined from the condition that the maximum breakdown voltage due to the one-dimensional field along the vertical path equals that of the lateral electric field along the surface. Analytical results agree well with the simulations using PISCES II, and qualitatively with the experimental results.

Interface states of modulation-doped AlGaAs/GaAs heterostructures

We have used the admittance spectroscopy to investigate interface states associated with heterojunction of modulation-doped AlGaAs/GaAs FETs. Anomalous frequency dispersion of the capacitance was observed. The results of the measurements were interpreted in terms of an equivalent circuit containing a series resistance of the two-dimensional electron gas in the ungated region between the gate and the source and drain electrodes. The maximum density of the interface states was found to be 1.3 × 1012cm-2. eV-1around 0.13 eV below the Ecedge of GaAs.

An analytical model for interaction of SIPOS layer with underlying silicon of SOI RESURF devices

An analytical model for interaction of semi-insulating polycrystalline silicon (SIPOS) layer with underlying silicon of SOI RESURF devices is presented which allows a clear picture of the potentials in the two regions coupled through the device parameters including the interface oxide thickness between the regions. The improvement in the breakdown voltage due to the presence of SIPOS layer is demonstrated, numerical simulations are shown to support the analytical model.

An Analytic Model of Planar Junctions with Multiple Floating Field Limiting Rings

Abstract A potential function satisfying the two-dimensional Poisson equation for planar junctions with a single field limiting ring(FLR) is presented for the first time which allows an approximate but quick determination of the breakdown voltage and optimized ring spacing. The problem of the multiple rings is then reduced to that of a single ring by means of the equivalent ring junction applied in sequence from the outmost ring. The results are in fair agreement with two-dimensional device simulations using MEDICI. Comparisons with experimental data reported for the optimum ring spacings and the relative improvement on the breakdown voltage of the FLR structure show the validity of the model. The present model is very useful for the FLR structure with multiple rings, providing a starting point for the numerical simulations.

An analytical method for two-dimensional field distribution of a MOS structure with a finite field plate

An analytical method is presented for two-dimensional field distribution of a MOS structure with a field plate, which allows explicit equations for field components in terms of oxide thickness, depletion width, and field plate length. Useful design curves of breakdown voltage versus substrate impurity concentration with oxide thickness and plate length as parameters are provided. >

Optimum design for minimum on-resistance of low voltage trench power MOSFET

An optimum trench width for the minimum on-resistance of a trench MOSFET (T-MOS) is determined analytically with the resistance contribution from the accumulation layer taken into account. Inclusion of the accumulation resistance is shown to be indispensable to the on-resistance of the T-MOS especially for a relatively large value of the trench width. The analytical results show a fair agreement with the numerical simulations using ATLAS.

Linearly-graded surface-doped SOI LDMOSFET with recessed source

Abstract A surface-doped SOI (Silicon-On-Insulator) LD (Lateral Double-diffused) MOSFET with a linearly-graded surface-doping profile is proposed which allows low on-resistance and high static and on-state breakdown voltage. The characteristics of the proposed LDMOS are verified by the two-dimensional process simulator TSUPREM4 and the device simulator, MEDICI. A reduction of the on-resistance by 83.4% from 62.9 Ω cm to 10.4 Ω cm and an increase in the static breakdown voltage from 146 V to 205 V and in the on-state breakdown voltage from 42 V to 96 V for a 10 V gate voltage are obtained for the proposed device when compared with those of the conventional one.