Yen Hung Kuo

Design and Analysis of a 77.3% Locking-Range Divide-by-4 Frequency Divider

A cascoded frequency divider (FD) with division number of 4 and ultra-wide locking range is presented in this paper. The proposed FD consists of a divide-by-2 (D2) injection-locked frequency divider (ILFD) core and a D2 source-injection current mode logic (SICML) divider. After the cascoded integration of ILFD and SICML, the removal of transconductance and buffer stages can lower the dc power consumption and widen the locking range. The proposed FD is implemented in 0.13-μm CMOS technology and has a 77.3% frequency locking range from 13.5 to 30.5 GHz at injection power of 0 dBm while consuming 7.3-mW dc power. Compared to the previously reported ILFDs, the proposed circuit achieves the widest locking range without employing extra tuning mechanism.

A 1.7-mW, 16.8% frequency tuning, 24-GHz transformer-based LC-VCO using 0.18-µm CMOS technology

A low-power, wide-tuning-range voltage-controlled oscillator (VCO) using 0.18-µm CMOS technology is presented in this paper. The proposed transformer-based LC-VCO has 16.8% frequency tuning range without switching techniques. To achieve wide-tuning-range and low-power in the same time, the current-reused topology is selected to demonstrate a low-power consumption of 1.7 mW. The VCO oscillation frequency at 22.6 GHz has a phase noise of −95dBc/Hz at 1 MHz offset.

Design and Analysis of Digital-Assisted Bandwidth-Enhanced Miller Divider in

A bandwidth-enhanced technique for a Miller divider is presented in this paper. The proposed frequency divider consists of a band-switched Miller divider and digital-assisted circuit to switch the resonator automatically. The proposed frequency divider is implemented in 0.18-μm CMOS technology and has a measured 57.4% bandwidth from 8.2 to 14.8 GHz at an input power of 0 dBm. The dc consumption is 12 mW. Compared to the previously reported Miller dividers, the proposed circuit achieves the widest fractional bandwidth.

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In this paper, a low-power transformer-based Ku-band receiver front-end is implemented in a 180-nm CMOS technology. The transformer-feedback gain-boosting technique and forward-body-bias technique are employed in three-stage (common gate + 2-stage common source) LNA to achieve a low-power design. A resistive ring mixer is chosen due to its advantage of zero-dc-power. The receiver demonstrates a 4.47-dB conversion gain at IF frequency of 100 MHz while consuming only 7.272 mW.

CMOS Process

We use the strategy method to conduct laboratory experiments on a nine‐player heterogeneous‐cost voting game. We replicate the underdog and competition effect, but find significantly higher voter turnout rates to be only partially explained by logit quantal response equilibrium. We examine round‐by‐round changes in cut‐off behaviour and find that voters are highly responsive to historical pivotal events. Voters also respond to past winning and tying, but only as a minority (upsetting the majority), demonstrating an ‘underdog winning effect’, receiving extra utility when winning as a minority. An equilibrium with such asymmetry in utility explains the high minority turnout (and high majority turnout as a best response).