Yen-Yi Lin

CDM peak current variations and impact upon CDM performance thresholds

Effect of device size on the peak CDM current is discussed. The current increases monotonically for small packages and then saturates for sizes larger than 1000 mm2. Size of the charge plate of the CDM tester contributed to this behavior. The current was not found to be constant across the package. Instead, it showed maximum value in the middle and minimum at the outer edge. An unexpected variation in CDM current is also reported for long pulse sequences.

An Insight into the High Current ESD Behavior of Drain Extended NMOS (DENMOS) Devices in Nanometer Scale CMOS Technologies

Second breakdown phenomenon (It2) in drain extended NMOS (DENMOS) which is associated with complex triggering of the parasitic BJT is relatively less understood. We present experiments and models to understand the physics of snapback in DENMOS in nanometer scale technologies. Avalanche injection phenomenon at the drain contact has been analyzed for a 90 nm DENMOS transistor under high current stressing

Linewidth control using anti-reflective coating for optical lithography

Several types of anti-reflective (AR) coating, including TiW, V, polysilicon films, and spun-on layer incorporated with an absorbing dye have been investigated to eliminate the light reflection from layers under resist. The exposure latitude can be widely extended by the AR coating. Both the standing wave effect and the linewidth change with respect to variation in exposure dose can also be reduced significantly. This simple and convenient technique can be effectively applied to reduce linewidth variations at step cross-over for wafers with vertical aluminum steps less than 0.8 µm height.