Joe Schichl

CDM peak current variations and impact upon CDM performance thresholds

Effect of device size on the peak CDM current is discussed. The current increases monotonically for small packages and then saturates for sizes larger than 1000 mm2. Size of the charge plate of the CDM tester contributed to this behavior. The current was not found to be constant across the package. Instead, it showed maximum value in the middle and minimum at the outer edge. An unexpected variation in CDM current is also reported for long pulse sequences.

Formation and suppression of a newly discovered secondary EOS event in HBM test systems

A previously undetected trailing pulse from HBM testers was found to create unexpected gate oxide failures on new technologies. This secondary pulse, which is EOS in nature, is caused by the discharge relay and the parasitics of the charge circuit. This paper investigates this critical phenomenon and establishes the tester improvements to safely suppress the trailing pulse effects.

A new I/O signal latchup phenomenon in voltage tolerant ESD protection circuits

We report for the first time a new type of unexpected latch-up phenomenon that can occur in deep sub-micron technologies with the required implementation of voltage tolerant ESD protection circuits. In contrast to the well known Standard latchup, this new latchup, dubbed Signal Latchup, becomes evident only through the interaction from neighboring I/O pins. The issues involved with this latchup effect and the subsequent trade-off with ESD are presented in detail. A new latchup specification is also proposed.