Yeng-Kaung Peng

Analysis of the impact of proximity correction algorithms on circuit performance

Variation in channel length degrades circuit reliability and yield. A common way to compensate for this problem is to increase the mean channel length, which, unfortunately, degrades circuit performance for digital circuits. One source of channel length variation is lithography, during which the line width is influenced by local layout patterns. It is possible to compensate for this effect by resizing transistor gates appropriately on the mask. However, the effectiveness of the correction is limited by constraints such as the mask correction resolution. To determine how to design a good correction scheme with limited resources, we have developed a method to compare different correction algorithms in terms of their impact on the performance of one of the main functional blocks in a state-of-the-art microprocessor. In particular, to evaluate correction algorithms while avoiding the high cost associated with generating multiple mask sets and fabricating product wafers with each of these mask sets, we present a method for predicting the correction results using simulation. Our methodology involves a DRC-based approach for gate resizing, along with critical path simulation for evaluating circuit performance. In-line CD measurement data were used to measure the impact of the proximity effect on transistor channel length. Electrical test results were used to calibrate the device models for circuit simulation.

Method of failure analysis with CAD layout navigation and FIB/SEM inspection

A method of analyzing a failure of a sample, such as a wafer or a package unit made from a die sliced from the wafer, uses a computer aided design (CAD) tool in conjunction with a dual beam scanner and reverse engineering to improve the yield of the product. The computer aided design tool provides navigation to a location of interest over a layout of a wafer sample which has failed a test. The location of interest of the sample is then inspected using the dual beam scanner. The inspection may be made with either a focused ion beam scan or with a scanning electron microscope scan to provide different types of scan images and information. After inspection, a reverse engineering process (stripping back) is performed on the sample and the sample is inspected again to determine the cause of the failure of the sample. Once the cause of the failure is determined, the manufacturing process can be changed to improve the yield of the wafers.

An analytical model of multiple ILD thickness variation induced by interaction of layout pattern and CMP process

In this paper, an analytical model for chemical mechanical polishing (CMP) is described. This model relates the physical parameters of the CMP process to the in-die variation of interlayer dielectric (ILD) in multilevel metal processes. The physical parameters considered in this model include the deposited ILD profile, deformation of the polishing pad and the hydrodynamic pressure of slurry flow. Model parameters are adjusted based on the first ILD layer and then applied to the upper ILD layers. Comparison of simulated results with sample data is performed at the die level of a state-of-the-art microprocessor.

Characterization of spatial CD variability, spatial mask-level correction, and improvement of circuit performance

Statistical characterization of gate CD variability of a production CMOS process reveals a large spatial intra-field component, strongly dependent on the local layout patterns. We present a novel measurement based characterization approach that is capable of capturing all the relevant CD variation patterns necessary for accurate circuit modeling and statistical design. A rigorous analysis of the impact of intra-field variability on circuit performance is undertaken. We show that intra-field CD variation has a significant detrimental effect on the overall circuit performance by reducing the average speed by up to 20 percent. We derive a model quantitatively relating intra- field CD variance delay degradation. We propose a mask-level spatial gate CD correction algorithm to reduce the intra- field and overall variability, resulting in circuit performance improvement, and provide an analytical model to evaluate the effectiveness of correction for variance reduction.

Proximity effect correction for clock-rate maximization

Deep submicron technology poses many difficult challenges. One of them is the optimization of the clock rate versus sub-threshold leakage trade-off. Top speed performance demands the shortest possible channel length for all transistors in the critical paths, while the need to limit subthreshold leakage requires that no transistor violates the minimum channel length rule. The problem is that the channel length is impacted by the layout density. One cause of variations in channel length is lithography. Since the global lithography settings must be chosen to avoid excessive subthreshold leakage, some of the transistors will have non-minimum channel lengths, and therefore will be slower than necessary. It is possible to compensate for the above effect by resizing transistors on the mask. In this paper we propose a methodology for analyzing different correction schemes in terms of their impact on critical path delays. Our methodology involves transistor categorization according to local layout patterns, together with simulation-based computations of channel length as a function of the local layout pattern. A DRC-based approach is used to identify transistor categories. Lithography simulation is used for proximity effect evaluation. Circuit speed is estimated by critical path simulation. In the paper we will compare various correction schemes for one of the main functional blocks in a a state-of-the-art microprocessor.