Charles H. Ouyang

In-line yield prediction methodologies using patterned wafer inspection information

Due to the advances in in-line inspection technology it is now possible to obtain an early in-line prediction of yield. This paper introduces and compares two new in-line yield prediction methodologies: (1) multilayer critical area method and (2) defect-type-size kill-ratio method. These methods are more accurate than the past and other current approaches used in the semiconductor industry. The first method uses the design layout information along with the in-line defect data, whereas the second method uses the defect and yield data to empirically derive the kill-ratios. We demonstrate our methodologies using data collected in a real wafer fabrication facility at the polysilicon gate (Poly), and the first and second interconnect (Metal 1 and Metal 2) post etch inspection layers. We compare our in-line predictions with the actual yield.

Analysis of the impact of proximity correction algorithms on circuit performance

Variation in channel length degrades circuit reliability and yield. A common way to compensate for this problem is to increase the mean channel length, which, unfortunately, degrades circuit performance for digital circuits. One source of channel length variation is lithography, during which the line width is influenced by local layout patterns. It is possible to compensate for this effect by resizing transistor gates appropriately on the mask. However, the effectiveness of the correction is limited by constraints such as the mask correction resolution. To determine how to design a good correction scheme with limited resources, we have developed a method to compare different correction algorithms in terms of their impact on the performance of one of the main functional blocks in a state-of-the-art microprocessor. In particular, to evaluate correction algorithms while avoiding the high cost associated with generating multiple mask sets and fabricating product wafers with each of these mask sets, we present a method for predicting the correction results using simulation. Our methodology involves a DRC-based approach for gate resizing, along with critical path simulation for evaluating circuit performance. In-line CD measurement data were used to measure the impact of the proximity effect on transistor channel length. Electrical test results were used to calibrate the device models for circuit simulation.

A DRC-based algorithm for extraction of critical areas for opens in large VLSI circuits

This paper describes an algorithm for the extraction of the critical area for opens. The presented algorithm allows for the analysis of industrial size ICs with non-Manhattan geometry. Illustrative examples of the proposed algorithm, implemented by using design rule checker operations, are presented. It is shown that the extraction of the critical area for realistic size VLSI circuits designs can be done in an acceptable time.

CAD at the design-manufacturing interface

Owing to rapid changes of IC technologies, traditionaldesign rule checking is becoming inadequate to assure satisfactorylevels of IC manufacturability. This paper describes a newcomputer supported design analysis environment that improvesthe efficiency of manufacturability assessment of new products.This environment, called MAPEX 2, is described in the paperalong with some of its key procedures and algorithms. Illustrationsof MAPEX 2 applications and performance figures are provided as well.

Extraction of critical areas for opens in large VLSI circuits

This paper describes a new algorithm for the extraction of the critical area for opens. The presented algorithm allows for the analysis of large ICs and non-Manhattan geometry. Concept of the contact/via contacting regions is proposed and its relevance is discussed. Illustrative examples of the proposed algorithm are presented.

An analytical model of multilevel ILD thickness variation induced by the interaction of layout pattern and CMP process

In this paper, an analytical model for Chemical Mechanical Polishing (CMP) is proposed. This model relates the physical parameters of the CMP process to the in-die variation of Inter-Layer Dielectric (ILD) in the multilevel metal process. The physical parameters considered in this model include the deposited ILD profile, deformation of the polishing pad and the hydrodynamic pressure of slurry flow. We demonstrate a fit with sample data at the die level of a state-of-the-art microprocessor.

Maximizing wafer productivity through layout optimizations

Success of the fabless model has increased competition and has put pressure on design houses to reduce die costs. One method of cost reduction is the application of design for manufacturability (DFM) at the layout stage. Previously DFM has been applied to standard cell libraries and has been shown to lower die cost by 4.6%. This paper applies DFM to the routing. In particular this paper analyzes the effects of various routing options on wafer productivity and shows that if properly applied DFM can lead to a further die cost reduction of 9%.

An analytical model of multiple ILD thickness variation induced by interaction of layout pattern and CMP process

In this paper, an analytical model for chemical mechanical polishing (CMP) is described. This model relates the physical parameters of the CMP process to the in-die variation of interlayer dielectric (ILD) in multilevel metal processes. The physical parameters considered in this model include the deposited ILD profile, deformation of the polishing pad and the hydrodynamic pressure of slurry flow. Model parameters are adjusted based on the first ILD layer and then applied to the upper ILD layers. Comparison of simulated results with sample data is performed at the die level of a state-of-the-art microprocessor.

Design-manufacturing interface. II. Applications [VLSI]

For pt. I see ibid., p. 550-6 (1998). This paper illustrates via examples problems at the design-manufacturing interface that exist in the IC industry today, and the ability of the YAN/PODEMA framework in solving these problems. The need for further development of the framework is also emphasized.

Proximity effect correction for clock-rate maximization

Deep submicron technology poses many difficult challenges. One of them is the optimization of the clock rate versus sub-threshold leakage trade-off. Top speed performance demands the shortest possible channel length for all transistors in the critical paths, while the need to limit subthreshold leakage requires that no transistor violates the minimum channel length rule. The problem is that the channel length is impacted by the layout density. One cause of variations in channel length is lithography. Since the global lithography settings must be chosen to avoid excessive subthreshold leakage, some of the transistors will have non-minimum channel lengths, and therefore will be slower than necessary. It is possible to compensate for the above effect by resizing transistors on the mask. In this paper we propose a methodology for analyzing different correction schemes in terms of their impact on critical path delays. Our methodology involves transistor categorization according to local layout patterns, together with simulation-based computations of channel length as a function of the local layout pattern. A DRC-based approach is used to identify transistor categories. Lithography simulation is used for proximity effect evaluation. Circuit speed is estimated by critical path simulation. In the paper we will compare various correction schemes for one of the main functional blocks in a a state-of-the-art microprocessor.