Ki-Whan Song

A New Capacitorless 1T DRAM Cell: Surrounding Gate MOSFET With Vertical Channel (SGVC Cell)

We propose a surrounding gate MOSFET with vertical channel (SGVC cell) as a 1T DRAM cell. To confirm the memory operation of the SGVC cell, we simulated its memory effect and fabricated the highly scalable SGVC cell. According to simulation and measurement results, the SGVC cell can operate as a 1T DRAM having a sufficiently large sensing margin. Also, due to its vertical channel structure and common source architecture, it can readily be made into a 4F2 cell array

55 nm capacitor-less 1T DRAM cell transistor with non-overlap structure

This paper presents a capacitor-less 1T DRAM cell transistor with high scalability and long retention time. It adopts gate to source/drain non-overlap structure to suppress junction leakage, which results in 80 ms retention time at 85degC with gate length of 55 nm. Compared to the previous reports, proposed cell transistor shows twice longer retention time even though the gate length shrinks to the half of them. By TCAD analysis, we have confirmed that the improvements are attributed to the superiority of the proposed device structure.

Silicon-based field-induced band-to-band tunnelling effect transistor

This letter reports a silicon-based field-induced band-to-band tunnelling effect transistor (FIBTET), which has a structure totally compatible with silicon-on-insulator (SOI) MOSFET. The field-induced band-to-band tunnelling effect between degenerate channel and source/drain is used as the key principle of the device operation. FIBTETs demonstrate the controllable negative differential transconductance characteristics at room temperature both for n-FIBTETs and p-FIBTETs. The size dependence of the device characteristics shows that the peak tunnelling current can be controlled by the layout design of channel length and width.

Design and optimization of two-bit double-gate nonvolatile memory cell for highly reliable operation

In this paper, characterization and optimization have been performed on the 2-b floating-gate-type nonvolatile memory (NVM) cell based on a double-gate (DG) MOSFET structure using two-dimensional numerical simulation. The thickness and the difference of charge amount between programmed and erased states are found to be the crucial factors that put the NVM cell operation under optimum condition. Under fairly good conditions, the silicon thickness can reach below 30 nm while suppressing the read disturbance level within 1 V. With these results, operating schemes are investigated for both NAND - and NOR-type memory cells. This paper is based on simulation works which can give a reasonable intuition in flash memory operation. Although we adopted a floating-gate-type device since the exact modeling of Si/sub 3/N/sub 4/ used for the storage node is absent in the current numerical simulator, this helps to predict the operation of an oxide-nitride-oxide dielectric flash memory cell at a good degree.

Field-induced interband tunneling effect transistor (FITET) with negative-differential transconductance and negative-differential conductance

The fabricated quantum-tunneling devices have a structure totally compatible with silicon-on-insulator CMOS device except for degenerate channel doping and the intentional omission of lightly doped drain (LDD) region. The key principle of the device operation is the field-induced interband tunneling effect, and thus the name of this quantum-tunneling device: FITET. In the transfer I-V characteristics of FITET, negative-differential transconductance (NDT) characteristics have been observed at room temperature. By controlling the critical device parameters to enhance field-effect such as gate oxide thickness, the peak-to-valley current ratio over 5 has been obtained at room temperature, and the negative-differential conductance (NDC) characteristics as well as NDT have been observed in the output I-V curves of the same FITET.

SET/CMOS hybrid process and multiband filtering circuits

We have developed an integration technology for the single electron transistor (SET)/CMOS hybrid systems. SET and CMOS transistors can be optimized without any possible degradation due to mixing dissimilar devices by adopting just one extra mask step for the separate gate oxidation (SGOX). We have confirmed that discrete devices show ideal characteristics required for the SET/CMOS hybrid systems. An SET shows obvious Coulomb oscillations with a 200-mV period and CMOS transistors show high voltage gain. Based on the hybrid process, new hybrid circuits, called periodic multiband filters, are proposed and successfully implemented. The new filter is designed to perform a filtering operation according to the periodic multiple blocking bands of which a period is originated from the SET. Such a novel function was implemented efficiently with a few transistors by making full use of the periodic nature of SET characteristics.

Realistic single-electron transistor modeling and novel CMOS/SET hybrid circuits

A practical single electron transistor (SET) model has been proposed with appropriate modifications to the previous analytical model. We have observed that non-ideal SET current behaviors such as turn-off and peak-to-valley ratio (PVCR) degradation is successfully reproduced by the new SET model. Based on the realistic SET model, we have developed a novel circuit scheme which enhances the stability of CMOS/SET hybrid logic. It is demonstrated that a universal literal gate with complementary self-biasing scheme operates quite well at high temperature in which the peak-to-valley current ratio of Coulomb oscillation degrades severely.

Complementary self-biased scheme for the robust design of CMOS/SET hybrid multi-valued logic

We propose a new technique to enhance the characteristics of CMOS/SET hybrid multi-valued logic (MVL) circuits in terms of their stability and performance. A complementary self-biasing method enables the SET/CMOS logic to operate perfectly well at high temperature in which the peak-to-valley current ratio of Coulomb oscillation severely decreases. The suggested scheme is evaluated by SPICE simulation with an analytical SET model, and it is confirmed that even SETs with a large Si island can be utilized efficiently in the multi-valued logic. We demonstrate a quantizer implemented by SETs with a 90-nm-long Si island on the basis of measured device characteristics and SPICE simulation, which shows high resolution and small linearity error characteristics.

Analytical modeling of field-induced interband tunneling-effect transistors and its application

In the room-temperature I-V characteristics of field-induced interband tunneling-effect transistors (FITETs), negative-differential conductance (NDC) characteristics as well as negative-differential transconductance (NDT) characteristics have been observed. The key operation principle of this quantum-tunneling device is the field-induced interband tunneling. To include the effect of interband tunneling, we have developed an analytical equation of interband tunneling current. Due to the inherent SOI-MOSFET structure of the FITET, the current equation of MOSFET has also been included in the analytical equation of the FITET. By comparing the calculated data from these two current components with the measured data, an additional excess tunneling current component has been introduced in the final analytical equation of the FITET. SPICE simulation results with this analytical model have shown good agreements with the experimental results. Also, this analytical model has been applied to verify the functionality of a simple digital logic gate such as XOR and four-level parity checker made by one FITET.

SOI MOSFET-based quantum tunneling device - FIBTET

We have previously reported the controllable complementary n- and p-type negative-differential transconductance (NDT) characteristics of a FIBTET (field-induced band-to-band tunneling effect transistor) on a degenerately doped SOI MOSFET. In this work, we investigate key parameters of device design and demonstrate negative-differential conductance (NDC) as well as NDT characteristics in FIBTETs, which have a structure totally compatible with SOI MOSFETs. the critical dose condition distinguishing FIBTET from MOSFET has been found and room temperature NDC as well as NDT was demonstrated in a SOI MOSFET compatible tunnel device. The NDC combined with NDT characteristics of FIBTETs will give room for various analog and digital circuit applications based on Si technology.