Pang-Jung Liu

A High-Efficiency CMOS DC-DC Converter With 9-

This paper presents an efficient CMOS dc-dc converter with fast transient recovery. A fast-transient control operating in conjunction with a linearly scaled gate-driving technique is used to concurrently improve the transient response and light-load efficiency of a dc-dc converter. The controller operates under a pulse-width modulation mode during steady state and enables a saturation mode during transient to attain fast transient response. The linearly scaled gate-driving technique optimizes the gate-driving voltage with respect to the changing load leading to lower gate-driving loss and better light-load efficiency. A prototype chip was implemented using a commercial 0.35-μm CMOS process to validate the proposed techniques. The measurement result shows a 5% increase in light-load efficiency and achieves an overall maximum efficiency of 90%. Moreover, the transient recovery time of a 450 mA step load change is less than 9 μs.

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This paper presents a spurious emission suppression technique for RF power amplifiers using frequency-hopping DC-DC converters. The frequency-hopping technique changes the switching frequency of the DC-DC converter dynamically and reduces the peak spur created by using a DC-DC converter with a radio frequency power amplifier. The use of this technique can also reduce the size of the external passive components used for reducing the ripple voltage of the DC-DC converter, which creates the radio frequency spurs. A prototype system using a cellular band power amplifier operating at 836.5 MHz and a commercial DC-DC converter was built to verify this technique. Measurement results show by frequency-hopping between eight frequencies, the maximum radio frequency spur can be reduced by more than 11 dB.

s Transient Recovery Time

This paper presents a novel dual-current pump module (DCPM) to improve the transient response of dc-dc converters. The DCPM operates only during transient to provide two additional current injections for step-up load and current drains for step-down load. Due to the two current pump paths, the current stress on the switches of the DCPM is also reduced. The measurement results show that the DCPM can enhance the dynamic recovery time of the buck dc-dc converter by more than an order.

A spurious emission reduction technique for power amplifiers using frequency hopping DC-DC converters

Techniques of a dual-path error amplifier and two capacitor multipliers for providing on-chip frequency compensation and soft-start function are proposed in this paper. The concept of the dual-path error amplifier is to use two currents to charge and discharge a compensation capacitor simultaneously. As a result, the equivalent capacitance is enlarged significantly with little additional power and silicon area. The dc-dc converter with the dual-path architecture also has great performance in transient response because the compensation capacitor is reduced significantly. For the soft-start function, the subtractive-type and time-average capacitor multipliers are used to relax the restriction of the capacitance and the charging current. Consequently, it is easy to integrate the soft-start capacitance into a chip and the output overshoot voltage can be suppressed. A prototype converter fabricated with TSMC 0.35-μm 2P4M CMOS process verifies the effectiveness of the techniques of a dual-path error amplifier and two capacitor multipliers. Experimental results demonstrate the converter stability, transient response, and soft-start function. The transient recovery time and transient ripple are less than 20 μs and 25 mV, respectively, for the load current swing from 50 to 500 mA. Moreover, the soft-start time is up to 8 ms. With the proposed techniques, the external pins of the dc-dc converters are minimized and their performance is improved significantly.

Dual-Current Pump Module for Transient Improvement of Step-Down DC–DC Converters

This paper presents an inductor current average control (ICAC) method that minimizes the undesirable transient glitches in dc-dc converters using a frequency-hopping pulsewidth modulation control. The analysis in this paper shows that without careful control of the frequency-hopping instant for the dc-dc converters, the transient glitches can be rather large in magnitude and may interfere with the modulated signal to be transmitted from a mobile communication device. The ICAC technique selects the frequency-hopping instant such that the average inductor current is undisturbed when the switching frequency hops. The measurement result shows that the ICAC technique can suppress the transient spurs by 14.1 dB and the voltage of the transient glitches by 65.3%.

Techniques of Dual-Path Error Amplifier and Capacitor Multiplier for On-Chip Compensation and Soft-Start Function

This paper presents a compact 10-bit digital-to-analog converter (DAC) for LCD source drivers. The cyclic DAC architecture is used to reduce the area of LCD column drivers when compared to the use of conventional resistor-string DACs. The current interpolation technique is proposed to perform gamma correction after D/A conversion. The gamma correction circuit is shared by four DAC channels using the interleave technique. A prototype 10-bit DAC with gamma correction function is implemented in 0.35 μm CMOS technology and its average die size per channel is 0.053 mm2, which is smaller than those of the R-DACs with gamma correction function. The settling time of the 10-bit DAC is 1 μs, and the maximum INL and DNL are 2.13 least significant bit (LSB) and 1.30 LSB, respectively.

Spur-Reduction Design of Frequency-Hopping DC–DC Converters

This paper shows that the optimal driving voltages of power MOSFETs can be well modeled by a linear function of the load current. Thanks to the linear model, the self-scaling gate drive technique is proposed to improve the light-load efficiency of DC-DC converters by reducing gate driving loss. The gate drive voltage is scaled dynamically with respect to load current change. The proposed self-scaling gate drive technique can attain about 5.8% incremental enhancement on light-load efficiency.

A 10-bit CMOS DAC With Current Interpolated Gamma Correction for LCD Source Drivers

This paper proposes a dual-transformer active-clamp forward converter (DT-ACFC) with nonlinear conversion ratio (NCR), which combines two forward converter units. Since only two active switches are needed, the cost and the circuit complexity can be lowered. To reduce switching loss, the proposed converter fulfills zero-voltage switching by employing the leakage inductance of the transformer and additional resonant inductance. By paralleling the transformer secondaries and changing the circuit architecture of each secondary side, we can make the output load current evenly shared among four output inductors such that the current stress and conduction losses of the output rectifiers can be decreased significantly. Moreover, the nonlinear step-down conversion ratio leads to a high duty utilization ratio for the proposed converter. Therefore, the DT-ACFC with NCR is suitable for applications of high output current and a wide input voltage range. Experimental results are shown to verify the theoretical analysis of the proposed forward converter.

A self-scaling gate drive technique for efficiency improvement of DC-DC converters

To reduce circuit complexity and better control the charging current for parallel charging, a switching-based charger with an adaptive hybrid duty cycle control (AHDCC) for multiple batteries is presented. Depending on the voltage difference of the batteries, the AHDCC mechanism automatically delivers a different amount of energy to each battery to realize battery voltage balance and reduce power losses. Since an intermittent charging method is adopted in the constant current (CC) mode, the effect of voltage drop across the batterys parasitic resistor can be removed, and thus the charging time in CC mode is prolonged. AHDCC adjusts the charging current, prolongs the charging period in CC mode, and entirely turns on the auxiliary switches in the constant voltage mode. As a result, the functionalities of fast charging and battery voltage balance can be realized concurrently. The experimental results demonstrate that the peak efficiency of the charger is up to 89.4% and the total charging time of two batteries is slightly smaller than that of a single battery.

A Dual-Transformer Active-Clamp Forward Converter With Nonlinear Conversion Ratio

A continuous-conduction mode (CCM) noninverting buck–boost (NBB) converter with a fast duty-cycle calculation (FDCC) control and duty-cycle locking strategy is proposed in this paper. Utilizing auxiliary and adjustable slopes of the modulation signal, the FDCC control not only rapidly determines an accurate duty cycle but also keeps the compensator output constant when the input voltage changes. The theoretical dc value of the numerator of the closed-loop line-to-output voltage transfer function is equal to zero whether the CCM NBB converter operates in boost or buck mode. It indicates that adopting the FDCC control can achieve ideal feedforward compensation for CCM buck and boost operations. Consequently, the output transient ripple of the CCM NBB converter with FDCC control can be eliminated significantly regardless of the unit-gain bandwidth of the NBB converter. To alleviate pulse skipping and to avoid changing buck and boost modes frequently, a duty-cycle locking method is adopted in the transition region of the buck and the boost. Hence, the duty-cycle locking method enhances power conversion and maintains the output voltage. The experimental results demonstrate that the proposed control schemes not only effectively reduce the line transient ripple but also obtain high efficiency in a wide range of input voltage.