Yi Zhang

A Micro-Power Two-Step Incremental Analog-to-Digital Converter

Integrated sensor interface circuits require energy-efficient high-resolution data converters. This paper proposes a two-step incremental A/D converter (IADC) which extends the performance of an Nth-order IADC close to that of a (2N-1)th-order IADC. The implemented device uses the circuitry of a second-order IADC (IADC2) to achieve close to third-order SNR performance. The proposed circuit does not require very high opamp DC gain; the gain can be as low as 60 dB for 100 dB SNR data conversion. The implemented IADC achieves a measured dynamic range of 99.8 dB, and an SNDR of 91 dB for a maximum input 2.2 VPP and a bandwidth of 250 Hz. Fabricated in 65 nm CMOS, the IADCs core area is 0.2 mm2, and it consumes only 10.7 μW. The measured FoMs are 0.76 pJ/conversion and 173.5 dB, both among the best reported results for IADCs. The measured results verify that the proposed two-step IADC is a more energy-efficient data conversion scheme than conventional high-order IADCs.

A 11μW 250 Hz BW two-step incremental ADC with 100 dB DR and 91 dB SNDR for integrated sensor interfaces.

A two-step incremental ADC (IADC) is proposed for low-bandwidth, micro-power sensor interface circuits. This architecture extends the order of a conventional IADC from N to (2N-1) by using a two-step operation, while requiring only the circuitry of an Nth-order IADC. The implemented third-order IADC achieves a measured dynamic range of 99.8 dB and an SNDR of 91 dB for a maximum input 2.2 VPP and 250 Hz bandwidth. Fabricated in 65 nm CMOS, the IADCs core area is 0.2 mm2, and consumes only 10.7 μW. The FoMs are 0.76 pJ/conversion-step and 173.5 dB, both among the best reported results.

Incremental Analog-to-Digital Converters for High-Resolution Energy-Efficient Sensor Interfaces

Integrated sensor interface circuits require power-efficient high-accuracy data converters. In many applications, the best choice is to use incremental A/D converters (IADCs) incorporating extended counting. In this paper, we discuss the operation and design of IADCs, including single-loop and MASH architectures. When using a direct-feed-forward modulator, the IADC accumulates the residue voltage, and it is easily to implement a hybrid scheme of extended counting. Several hybrid schemes are review and discussed. A multi-step extended counting scheme is discussed for high-resolution power-efficient conversion. Optimal trade-off between high order and high oversampling ratio is critical for energy efficiency. A two-step IADC is discussed, which extends the performance of an Nth-order IADC close to that of a (2N-1)th-order IADC, with reduced power. An implemented device uses the circuitry of a second-order IADC (IADC2) to achieve a performance close to that of a third-order IADC. The two-step operation can be extended to multi-step one, and the SQNR performance can be increased significantly. The two-step operation can be extended to multi-step operation, which can boost up the order of SQNR and further improve the energy efficiency drastically.

A 16-bit 1KHz bandwidth micro-power multi-step incremental ADC for multi-channel sensor interface

In this paper, a micro-power three-step Incremental ADC (IDC) is presented. The proposed IDC achieves an equivalent order of six, realized by only three integrators. Compared to traditional IDCs, the proposed topology can be more power-efficient by implemented with the very low Oversampling Ratio (OSR).

A Continuous-Time Delta-Sigma Modulator for Biomedical Ultrasound Beamformer Using Digital ELD Compensation and FIR Feedback

This paper presents the design of a continuous-time ΔΣ modulator (CTDSM) to be used in an ultrasound beamformer for biomedical imaging. To achieve better resolution, the prototype modulator operates at 1.2 GHz. It incorporates a digital excess loop delay (ELD) compensation to replace the active adder in front of the internal quantizer. A digitally controlled reference-switching matrix, combined with the data-weighted averaging (DWA) technique, results in a delay-free feedback path. A multi-bit FIR feedback DAC, along with its compensation path, is used to achieve lower clock jitter sensitivity and better loop filter linearity. The modulator achieves 79.4 dB dynamic range, 77.3 dB SNR, and 74.3 dB SNDR over a 15 MHz signal bandwidth. Fabricated in a 65 nm CMOS process, the core modulator occupies an area of only 0.16 mm2 and dissipates 6.96 mW from a 1 V supply. A 58.6 fJ/conversion-step figure of merit is achieved.

Low-Distortion Wideband Delta-Sigma ADCs With Shifted Loop Delays

This paper presents several novel low-power low-distortion ΔΣ modulator topologies with shifted loop delays. Both single-sampled and double-sampled modulators are discussed. The proposed architectures can relax the critical timing for quantization and for dynamic element matching. A delay-free integrator in the last stage is used to perform the active summation, hence eliminating the active adder. The reduced input swing of the last integrator relaxes the OTAs requirements. The proposed topology simplifies the feed-forward paths, and saves power consumption and capacitor area. Noise-coupled technique can also be utilized to enhance the noise shaping. To verify the effect of the proposed topology, single- and double-sampled third-order ΔΣ modulators with and without noise coupling were analyzed and simulated.

A 35µW 96.8dB SNDR 1 kHz BW multi-step incremental ADC using multi-slope extended counting with a single integrator

A multi-step incremental ADC (IADC) with multi-slope extended counting is presented. In the proposed IADC, the accuracy is enhanced by reconfiguring it as a multi-slope ADC in two additional steps. For the same accuracy, the conversion cycle is shortened by a factor of about 29 as compared to the single-step IADC. Fabricated in 0.18-μm CMOS process, the prototype ADC operates at 642 kHz and achieves a peak SNDR = 96.8 dB and DR = 99.7 dB over a 1 kHz bandwidth. The power consumption is 35 μW, which results in an excellent Schreier FoM of 174.6 dB.

A noise-coupled low-distortion delta-sigma ADC with shifted loop delays

A low-power low-distortion ΔΣ ADC topology with shifted loop delays is proposed. Compared to the conventional low-distortion modulator, this topology can relax the critical timing for quantization and DEM by shifting the loop delay from the last integrator to the feedback path. Also, by adding one more feedback path, the last integrator can achieve both integration and active summation. Noise-coupled technique can also be utilized in the proposed modulator. To verify the effectiveness of this topology, a third-order noise-coupled ΔΣ modulator is analyzed and simulated.

A 1 V 59 fJ/Step 15 MHz BW 74 dB SNDR continuous-time ΔΣ modulator with digital ELD compensation and multi-bit FIR feedback

A 3rd-order continuous-time ΔΣ modulator with a highly-digital excess loop delay compensation and multi-bit FIR feedback, to be used in an ultrasound beamformer, is presented. A digitally controlled reference switching matrix avoids the power-hungry adder, and allows a power-efficient design of the loop filter. A 2-bit 3-tap FIR feedback DAC optimally achieves lower sensitivity to clock jitter and applies reduced error signal to the loop filter, thus enhancing the loop filter linearity. The modulator operates at 1.2 GHz, and achieves 79.4 dB dynamic range, 77.3 dB SNR and 74.3 dB SNDR over a 15 MHz signal bandwidth. Fabricated in a 65 nm CMOS process, the core modulator occupies 0.16 mm2 and dissipates 6.96mW from a 1 V supply. A 58.6 fJ/conversion-step figure of merit is achieved.

An incremental analog-to-digital converter with multi-step extended counting for sensor interfaces

Integrated sensor interface circuits require power-efficient high-accuracy data converters. In many applications, the best choice is the incremental A/D converters (IADCs) incorporating extended counting. In this paper, we discuss the operation and design of single- and multi-stage IADCs. By using a direct-input feed-forward modulator, the IADC accumulates the residue voltage, and it is easy to implement a hybrid scheme of extended counting. Several hybrid schemes are reviewed and discussed. The energy efficiency c an be improved significantly by re-using the hardware to perform extended counting. A multi-step extended counting scheme is proposed for high-resolution power-efficient conversion. A design example with OSR=320 is described in this paper. By using multi-step extended counting, the SQNR performance is boosted to 108 dB, which is much better than that of a second-order IADC of the same OSR, 94 dB.