Kazuki Sobue

Ring amplifiers for switched-capacitor circuits

In this paper the fundamental concept of ring amplification is introduced and explored. Ring amplifiers enable efficient amplification in scaled environments, and possess the benefits of efficient slew-based charging, rapid stabilization, compression-immunity (inherent rail-to-rail output swing), and performance that scales with process technology. A basic operational theory is established, and the core benefits of this technique are identified. Measured results from two separate ring amplifier based pipelined ADCs are presented. The first prototype IC, a simple 10.5-bit, 61.5 dB SNDR pipelined ADC which uses only ring amplifiers, is used to demonstrate the core benefits. The second fabricated IC presented is a high-resolution pipelined ADC which employs the technique of Split-CLS to perform efficient, accurate amplification aided by ring amplifiers. The 15-bit ADC is implemented in a 0.18 μm CMOS technology and achieves 76.8 dB SNDR and 95.4 dB SFDR at 20 Msps while consuming 5.1 mW, achieving a FoM of 45 fJ/conversion-step.

A 61.5dB SNDR pipelined ADC using simple highly-scalable ring amplifiers

A ring amplifier based pipelined ADC is presented that uses simple cells constructed from small inverters and capacitors to perform amplification. The basic ring amplifier structure is characterized and demonstrated to be highly scalable, power efficient, and compression-immune (inherent rail-to-rail output swing). The prototype 10.5-bit ADC, fabricated in 0.18μm CMOS technology, achieves 61.5dB SNDR at a 30MHz sampling rate and consumes 2.6mW, resulting in a FoM of 90fJ/conversion-step.

Parallel gain enhancement technique for switched-capacitor circuits

This paper presents a unified classification model for gain enhancement techniques used in the design of high performance amplifiers. A parallel gain enhancement technique is proposed for switched capacitor circuits which combine the best features of the existing gain enhancement techniques found in continuous-time and discrete-time amplifiers. This technique utilizes two dependent closed loop amplifiers to enhance the open loop DC gain of the main amplifier. This replicated parallel gain enhancement (RPGE) technique enables a very high DC gain amplifier with an improved harmonic distortion performance. A proof of concept pipeline ADC in a 0.18 um CMOS process using RPGE technique achieves 75 dB SNDR, 91 dB SFDR, -87 dB THD at 20 MS/s. The measured 13 bit DNL and INL is +0.75/-0.36 and +0.88/-0.92 LSB respectively. The ADC operates from a supply voltage of 1.3 V, consumes 5.9 mW, occupies 3.06 mm2 and achieves a figure of merit of 65 fJ/CS.

An 11-Bit 250-nW 10-kS/s SAR ADC With Doubled Input Range for Biomedical Applications

This paper presents a low power, area efficient 11bit single-ended successive-approximation-register (SAR) analog-to-digital converter (ADC) with small loading effect targeted for biomedical applications. The design features an energy-efficient switching technique with an error cancelling capacitor network to cover an input range twice the reference voltage. The ADCs loading effect to previous stage is reduced by using single-ended structure and eliminating the largest capacitor in switching network. The common-mode voltage of the input signal, generated by other blocks, can be used as reference voltage. All building blocks were designed in subthreshold for power efficiency, with asynchronous self-controlled SAR logic. The ADC was fabricated in a 0.18 μm CMOS 2P4M process. The measured peak SNDR was 60.5 dB, the SFDR was 72 dB, the DNL +0.6/−0.37 LSB and the INL +0.94/−0.89 LSB. The total power consumption was 250 nW from a 0.75 V supply voltage.

A 48 fJ/CS, 74 dB SNDR, 87 dB SFDR, 85 dB THD, 30 MS/s pipelined ADC using hybrid dynamic amplifier

A hybrid dynamic amplifier is proposed which combines the desirable features of a dynamic amplifier and a class AB amplifier. This technique allows us to achieve a power efficient high resolution pipeline ADC. A proof of concept pipelined ADC in a 0.18 μm CMOS process achieves 74.2 dB SNDR, 87 dB SFDR and 85 dB THD at 30 MS/s. The pipeline ADC consumes 6 mW from a 1.3 V supply and occupies 3.06 mm2. The ADC achieves a FoM of 48 fJ/CS without any form of calibration.

A 0.951 ps rms period jitter, 3.2% modulation range, DSM-free, spread-spectrum PLL

This work presents a delta-sigma modulator free in-loop-bandwidth spread-spectrum clock generator. The proposed charge-based discrete-time loop filter with a digital-to-current converter enables wide range spread-spectrum frequency modulation with significantly relaxed PVT sensitivity. A correlated double sampling technique is leveraged to minimize 1/f noise in the proposed discrete-time loop filter. This work achieves 3.2% spread-spectrum modulation range and 26.51dB spectrum attenuation at 352MHz output frequency. A 142% change in KVCO results in less than 298ppm modulation range error. Implemented in a 0.18μm CMOS, this work achieves 951fsrms period jitter while consuming 9.93mW with a 1.8V supply.

A two-capacitor SAR-assisted multi-step incremental ADC with a single amplifier achieving 96.6 dB SNDR over 1.2 kHz BW

This paper presents a two-step incremental ADC (lADC) using extended counting. In the first step, the lADC is configured as a first-order ΔΣ loop with an input feedforward architecture. In the second step, a two-capacitor SAR-assisted extended counting technique enhances the accuracy. A single active integrator is shared in both steps. Fabricated in 0.18-μm CMOS process, the IADC achieves a peak SNR/SNDR/DR of 97.1/96.6/100.2 dB over a 1.2 kHz bandwidth, while dissipating 33.2 μW from a 1.5 V supply. This gives a Schreier FoM of 175.8 dB and Walden FoM of 0.25 pJ/conv.-step, both among the best values.

A power efficient PLL with in-loop-bandwidth spread-spectrum modulation scheme using a charge-based discrete-time loop filter

This paper presents an in-loop-bandwidth spread-spectrum clock generation by proposing a linear charge-based discrete-time loop filter. The proposed architecture achieves a power efficient (2.29mA/GHz) spread-spectrum modulation scheme based upon a conventional CP-PLL. This work supports a modulation range of +/−2.7 % of a 700 MHz output frequency with the modulation rate in the range of 10 ∼ 100 kHz. The measured period rms and peak-to-peak jitters are 2.71 ps, rms and 20.6 ps, pp, respectively. The proposed spread-spectrum clock generator is fabricated in a 180 nm CMOS process and occupies an area of 0.525 mm2.

A 50 MHz bandwidth 54.2 dB SNDR reference-free stochastic ADC using VCO-based quantizers

A reference-free stochastic ADC is proposed by utilizing both spatial averaging and oversampling noise-shaping schemes. By implementing multiple VCO-based quantizers in parallel, stochastic spatial averaging for quantization errors is inherently obtained. In addition, 1st-order noise shaping of a VCO-based quantizer is achieved in an open-loop oversampling configuration. By resolving a faster conversion rate, this open-loop structure eliminates biasing, loop filter, sample-and-hold, and external reference, and it consists of only delay cells and digital logic. The proof-of-concept prototype which includes eight VCO-based quantizers and spatial averaging estimator is implemented in a 0.18 μm CMOS process, demonstrating 54.2 dB and 45.4 dB SNDR for 50 MHz and 100 MHz bandwidths, with 116 mW power consumption. Measurement results reveal that the eight channel stochastic ADC provides an average 9 dB SQNR improvement due to the spatial averaging.

A 19.2-mW, 81.6-dB SNDR, 4-MHz bandwidth delta-sigma modulator with shifted loop delays

A third-order switched-capacitor low-distortion delta-sigma ADC with shifted loop delays (SLD) is described, and its performance is discussed. It can relax the speed requirements of the quantizer and the dynamic element matching (DEM) block, and eliminate the last stage adder. An implemented 0.18 um CMOS prototype with the proposed architecture provided 81.6 dB SNDR, 81.8 dB dynamic range, and -95.6 dB THD in a signal bandwidth of 4 MHz. It dissipates 19.2 mW with a 1.6 V power supply. The conventional low-distortion ADC was also implemented on the same chip for comparison. The new circuit has superior performance, and dissipates 25% less power (19.2 mW vs. 24.9 mW) than the conventional one. The figure-of-merit for the ADC with SLD is among the best reported for wideband discrete-time ADCs, and is almost 40% better than that of the conventional ADC.