Yifeng Chen

Phase change memory based on Ge2Sb2Te5 capped between polygermanium layers

The effects of polygermanium interlayer, acting mainly as heating and thermal-resisting one, on performance of phase change memory are studied. Thermal simulation shows that the maximum temperature in Ge2Sb2Te5 layer is remarkably promoted when Ge2Sb2Te5 is capped between polygermanium layers. The maximum temperature location moves closer to the interface between Ge2Sb2Te5 and tungsten plug, significantly avoiding the parallel resistance in the reset state, which makes the memory more reliable. Electrical measurement shows that the polygermanium capped structure has a much lower reset current and larger resistance contrast compared to the one without polygermanium layers.

An 8-Mb Phase-Change Random Access Memory Chip Based on a Resistor-on-Via-Stacked-Plug Storage Cell

In this letter, an 8-Mb phase-change random access memory (PCRAM) chip has been developed in a 130-nm 4-ML standard CMOS technology based on a Resistor-on-Via-stacked-Plug (RVP) storage cell structure. This phase-change resistor is formed after CMOS logic fabrication. PCRAM can be embedded without changing any logic device and process. The memory cell selector is implemented by a standard 1.2-V nMOS device. The currents of the set and reset operations are 0.4 and 2.2 mA, respectively. The best endurance is over 1010 cycles.

RESET Distribution Improvement of Phase Change Memory: The Impact of Pre-Programming

Some nonvolatile phase change memory (PCM) cells with 80-nm heating electrodes are found very difficult to RESET at 3 mA, which directly affects the RESET distribution of the PCM. The large crystal grains with hexagonal structure in the active phase change area, discovered by transmission electron microscope, are the major reason. One preprogramming testing method is introduced, and the resistance distributions of the PCM cells before and after preprogramming are presented. Results show that the large hexagonal crystal grains have been eliminated, thus the resistance distributions have been greatly improved after preprogramming.

Understanding the early cycling evolution behaviors for phase change memory application

The RESET current of T-shaped phase change memory cells with 35 nm heating electrodes has been studied to understand the behavior of early cycling evolution. Results show that the RESET current has been significantly reduced after the early cycling evolution (1st RESET) operation. Compared the transmission electron microscope images, it is found that the hexagonal Ge2Sb2Te5 (GST) crystal grains are changed into the grains with face centered cubic structure after the early cycling evolution operation, which is taken as the major reason for the reduced RESET current, confirmed by a two-dimensional finite analysis and ab initio calculations.

Optimization of periphery circuits in a 1K-bit PCRAM chip for highly reliable write and read operations

A 1K-bit phase change random access memory (PCRAM) with improved periphery circuits for better reliable operations has been successfully developed in 130 nm CMOS technology. A flexible write driver is proposed to provide a novel continuous step-down pulses by studying programming strategies while a reliable read circuit is designed by investigating the special transition characteristics of PCRAM, leading to an effective write operation and a non-destructive read operation without any additional changes of the storage states. In addition, a large sense margin has been achieved and the read results corresponding well with the write operations, which demonstrate the influences of technology variations have been considerably decreased with the proposed periphery circuits.

Methods to speed up read operation in a 64 Mbit phase change memory chip

A 64Mbit phase change memory chip is fabricated in 40 nm CMOS technology. An improved fully-differential sense amplifier with a bias voltage instead of the reference resistor branch is proposed to diminish the chip area. The transient response capability of the proposed sense amplifier is improved by removing the large parasitic capacitance of bit line in the feedback network. Smaller parasitic capacitance is also obtained by the separated programming and reading transmission gates to speed up the read operation. The hierarchical bit line architecture is used to reduce the length of bit line, and thus favorable read performance can be achieved.

Current Controlled Relaxation Oscillations in Ge2Sb2Te5-Based Phase Change Memory Devices*

The relaxation oscillation of the phase change memory (PCM) devices based on the Ge2Sb2Te5 material is investigated by applying square current pulses. The current pulses with different amplitudes could be accurately given by the independently designed current testing system. The relaxation oscillation across the PCM device could be measured using an oscilloscope. The oscillation duration decreases with time, showing an inner link with the shrinking threshold voltage Vth. However, the relaxation oscillation would not terminate until the remaining voltage Von reaches the holding voltage Vh. This demonstrates that the relaxation oscillation might be controlled by Von. The increasing current amplitudes could only quicken the oscillation velocity but not be able to eliminate it, which indicates that the relaxation oscillation might be an inherent behavior for the PCM cell.

A Low-Power 1Kb PCRAM Chip with Elevated Write Performance

A low-power 1Kb phase change random access memory (PCRAM) chip is designed. The chip uses 1T1R (one transistor one resistor) structure and titanium nitride (TiN) bottom electrode (BE) for reducing power consumption. Besides, the write property of the chip is improved by employing a ramp down pulse generator. The chip is fabricated in 130nm CMOS standard technology. The test result shows a 56% power reduction based on TiN BE compared with tungsten (W) BE, which predicts a new direction to realize the commercialization of PCRAM.

Optimization of Anomalous Cells with High SET Resistance in Phase Change Memory Arrays

The resistance distribution in the crystalline (SET) state of phase change memory (PCM) is experimentally investigated at the array level using an 8 Mbit test chip. The SET distribution shows a high resistance tail, which potentially affects the reading margin of the chip. To further understand the anomalous behaviors of these tail cells, the SET resistances are characterized in terms of the programming pulse current magnitude and duration. These tail cells are probably caused by incomplete crystallization of the inactive region of phase change material. Finally, an optimization approach of applying a direct current of 0.6 mA to these tail cells is proposed and experimentally verified.

Test system of current pulse in phase change memory devices

Up to now, there is no direct test system of current pulse in phase change memory (PCM). The traditional test system uses direct current or voltage pulses to do the set operation and voltage pulses to do reset operation. In this work, a new test system is introduced. This system can give current source pulses to the PCM device to do set operation. The test results are presented and analyzed.