Yiqun Wei

Derivative superposition method for DG MOSFET application to RF mixer

A high linear double-gate (DG) MOSFET application to RF mixer is proposed based on derivative superposition method which was successfully used in Bulk CMOS region. By independently biasing front and back gate voltage of DG MOSFET, one DG MOSFET device is reviewed as two parallel devices. In this way, we realize the derivative superposition method application in the DG MOSFET linearity analysis and high performance RF mixer. Via two-dimensional (2D) TCAD device simulation and through the third-order transconductance (gm3) cancellation, we get some interesting results of DG MOSFET mixer different from the Bulk CMOS mixer. It is found that the DG MOSFET is suitable to work as a single device mixer because of coupling effect of two gates, e.g., a high linear independent DG MOSFET mixer shows 7.8dB improvement on IIP3 corresponding to the symmetrical DG mixer with the same DC current. The relationships between the amplitude of LO signal, the conversion gain and linearity are also analyzed in this paper.

FinFET reliability study by forward gated-diode generation-recombination current

Reliability of FinFETs is studied in this paper using the forward gated-diode generation–recombination (G–R) current. The current–voltage characteristics of a FinFET are measured for parameter extraction and a mathematical algorithm is used to extract the stress-induced interface states and oxide traps of the FinFET from the G–R current measurement. It is observed that the stress-induced interface states and oxide traps can be distinguished by observing the shift of the peak G–R current in the body current (Ib) versus gate voltage (Vg) characteristic. The interface states cause a change in the maximum G–R current (ΔIpeak) while the oxide traps result in a shift of the gate voltage (ΔVg) corresponding to the ΔIpeak. Unlike bulk MOSFETs, the dominant degradation mechanism of FinFETs is found to be the oxide traps formation rather than the interface states generation.

A compact model for phase change memory based on carrier transport mechanism

In this paper, a compact model for phase change memory (PCM) based on carrier transport mechanism is presented. In this model, the set and reset resistances of the cell are calculated through the traditional transport theory and the hopping transport theory respectively, coupling with the temperature and the phase-change kinetics calculation. With the temperature-sensing and storage module embeded, this model is effective in partial crystallization condition. The I–V performance and the R-I status are calibrated by experimental data and numerical simulation. This model is implemented in Verilog-A, making it easily applied to many circuit level simulation tools and useful to PCM design.

Numerical simulation of programming and read process for nano-scale phase-change memory (PCM) cell

As one of the candidates of the next generation non-volatile memory(NVM), phase change memory(PCM) has been paid more attention. However, there are still many open issues such as numerical simulation to study. Phase transition is a temperature based process, which can be simulated by temperature profile generated by the device simulator coupled with the phase transition model. In this work, a phase transition model is implemented, which can provide the amorphization process simulation and the nucleation process simulation, and the set and reset process are simulated. Meanwhile the readout I-V characteristics are simulated and discussed.

Carrier-based compact modeling of charge and capacitance of long channel undoped symmetric double-gate MOSFETs

Carrier-based compact modeling of terminal charges and intrinsic trans-capacitances of a long channel undoped symmetric double-gate MOSFET is presented in this paper. The explicit expressions for the terminal charges are obtained from a simplified carrier-based drain current model and the current continuity principle. Then analytic trans-capacitances are derived in terms of the charges at the source and drain ends. The validity of the analytic terminal charges and trans-capacitances is also verified by 2D numerical analysis proving the accuracy of the compact model presented here.

A data retention model for phase-change memory by the Monte Carlo approach

Data retention is an important issue in the phase-change memories (PCMs) development, which is induced by the spontaneous thermal-driven crystallization for amorphous phase of chalcogenide material in PCMs. In this work, a data retention model for PCMs induced by spontaneous crystallization is presented. In this model, the spontaneous crystallization mechanism is modeled by nucleation and growth (N/G) theory, and Monte-Carlo approach is introduced to model the N/G process due to the stochastic nature of nucleation. According to this model, the resistance evolution with time is calculated. The model is calibrated by the experimental data, and results fit experimental data well. By defining the failure resistance, the statistical distributions of retention failure times are calculated, and the retention characteristics of PCMs are predicted.

A compact model of diode array for Phase Change Memory

In this paper, a compact diode array model for Phase Change Memory (PCM) application is presented. From the diode array structure and numerical simulation result, a quasi-physical compact model is proposed by combining the classical diode equation and simplified bipolar device formulation. This model results in accurate calculation of different leakage current components with parameter setting. Furthermore, the presented model is an open model structure, and can be applied in different fabrication process with the parameter extraction. All these characteristics make it useful in further study of physical mechanism of carrier transmissions in order to illustrate the device physics of such an array diode device.

A Snake Addressing Scheme for Phase Change Memory Testing

Phase change memory (PCM) is one of the most promising candidates for next generation nonvolatile memory. However, PCM suffers from a variety of faults due to its special device structure and operation mechanism. A snake addressing scheme is introduced into the test algorithms of PCM to reduce the test time and excite proximity disturb faults more effectively. The March test algorithm with the proposed snake addressing scheme is less complex than most traditional test algorithms. In addition to conventional faults, it is capable of covering disturb and parasitic faults. Moreover, when incorporated with the sneak path testing method, it is able to test the read fault, read recovery fault, incomplete program fault 0, and false write fault.摘要中文概要相变存储器是一种新型非易失存储器。由于其特殊的器件特性和操作机制, 相变存储器可能发生多种类型的故障。本文设计了一种面向相变存储器测试的蛇形寻址方法, 可更加有效地激活相变存储器中的热串扰故障, 并利于减少测试时间。引入蛇形寻址方法的March测试算法, 可有效覆盖十种相变存储器故障类型, 且可将测试复杂度降低至7mn。引入蛇形寻址方法的潜通路测试算法可进而将测试复杂度降低至4.95mn, 并仍可覆盖十种相变存储器故障类型。创新点1、设计了一种面向相变存储器测试的蛇形寻址方法, 可更加有效的激活相变存储器的热串扰故障。2、应用蛇形寻址方法, 设计了一种相变存储器阵列的March测试算法, 可有效覆盖十种相变存储器故障, 并将算法复杂度降至7mn。3、应用蛇形寻址方法, 设计了一种相变存储器阵列的潜通路测试算法, 用4.95mn的算法复杂度代价有效覆盖十种相变存储器故障。

A three-dimensional numerical simulator of phase-change memory by random nucleation and growth approach

Due to restricted dimensions, the two-dimensional structure is not able to simulated one special geometry precisely, such as the asymmetric heater structure, Edge contact and u-trench structures. In this paper, a real 3d numerical model based on the finite element method for phase change random access memory is developed. Study on the phase change by using the heat-transfer equations, Laplace equation and Monte Carlo method based on the nucleation and growth theory [1]. Some heater with different shapes is simulated in this paper. The temperature distribution, phase fraction profiles I-R curves and I-V curves can be simulated respectively. By analyzing the programming properties of cells at different device structure, programming current and time, the impacts of the reset current to the programming characteristics are evaluated.

Electronic and electrothermal switching dynamics in chalcogenide-based phase-change memory (PCM)

Towards reliability optimization of chalcogenide-based phase-change memory cells, the study on transport and phase-transition models are necessary. A threshold switch model based on the hopping transport mechanism and the field-assisted trap-to-band excitation mechanism is presented, accounting for the scaling dependence of the threshold voltage and current. The read reliability issues related to the structure relaxation effect are discussed using this model. A phase switch algorithm based on the nucleation-growth theory and Monte-Carlo method is achieved, which is able to model the random nuclei generation and growth progress including interface effect. Through the simulations of nucleation dominant material and growth dominant material, the prospect of nucleation-growth phenomenon is shown. The data retention capability is evaluated by the model.