Yoichi Taira

Sequential-color LCD based on OCB with an LED backlight

We have fabricated a 13.3-in. XGA (1024 × 768) TFT sequential-color liquid-crystal display using optically compensated birefringency (OCB), illuminated by an LED backlight. We fabricated the sequential-color display feasible process technology, and examined the performance and potential of a field-sequential-color scheme. The display was connected to a laptop computer and examined for flicker.

Dot pattern generation technique using molecular dynamics

We have developed a new technique for generating homogeneously distributed irregular dot patterns useful for optical devices and digital halftoning technologies. To introduce irregularity, we use elaborately designed sequences called low-discrepancy sequences instead of pseudorandom numbers. We also use a molecular-dynamics redistribution method to improve the distribution of dots. Our method can produce arbitrary density distributions in accordance with a given design. The generated patterns are free from visible roughness as well as any moiré patterns when superimposed on other regular patterns. We demonstrate that our method effectively improves luminance uniformity and eliminates moiré patterns when used for a backlight unit of a liquid-crystal display.

52.2: Invited Paper: Color Sequential LCD Based on OCB with an LED Backlight

We have fabricated a 13.3″ XGA (1024 by 768) TFT color sequential liquid crystal display using Optically Compensated Birefringency (OCB), illuminated by an LED backlight. We fabricated the color sequential display using mostly feasible process technology, and examined the performance and potential of a color field sequential scheme. The display was connected to a laptop computer and examined for flicker perception.

Low-Cost Interfacing of Fibers to Nanophotonic Waveguides: Design for Fabrication and Assembly Tolerances

The high cost and low scalability of interfacing standard optical fibers to nanophotonic waveguides hinder the deployment of silicon photonics. We propose a mechanically compliant low-cost interface with integrated polymer waveguides. Our concept promises better mechanical reliability than a direct fiber-to-chip coupling and a dramatically larger bandwidth than diffractive couplers. Our computations show a 0.1-dB penalty over a 200-nm bandwidth, whereas typical two-polarization vertical couplers show a ~1-dB penalty over a 30-nm bandwidth. In this paper, we present a comprehensive analysis of the design space using optimization routines to achieve a fabrication- and assembly-tolerant design. We demonstrate the concept feasibility through extensive tolerance analysis with parameter control assumptions derived from low-cost manufacturing.

Thermal resistance measurements of interconnections, for the investigation of the thermal resistance of a three-dimensional (3D) chip stack

As device-scaling challenges increase, three-dimensional (3D) integrated circuits (ICs) are receiving more attention for system performance enhancements, due to their higher interconnect densities and shorter interconnect lengths. However, because of the limited contact area and the higher circuit density, the cooling of 3D ICs is more challenging. In order to assess appropriate cooling solutions for 3D chip stacks in various uses, we need better understanding of the total thermal resistance of 3D chip stacks. This calls for precise thermal resistance measurements and thermal modeling for each component of a 3D chip stack. A 3D chip stack is composed of interconnections, silicon substrates, back-end-of-the-line (BEOL), front-end-of-the-line (FEOL) and in this study, the thermal resistance of interconnections is the primary focus because interconnections are regarded as one of the thermal resistance bottlenecks of a 3D chip stack. With regard to the thermal resistance measurements of interconnections, Yamaji et al. found it difficult to measure the thermal resistance of interconnections with the laser-flash method and pointed out that care was necessary for uniform temperature distribution in the sample when using the laser-flash method on heterogeneous specimens, such as stacked chips with interconnections. Considering this concern, we use a steady-state method for the thermal resistance measurements of the interconnections. The thermal resistance of 200μpitch-C4 (Pb97Sn3) joined samples is measured and the thermal conductivity of C4 is derived to be 18 – 24 W/mC. Also the thermal resistance of a silicon with various interconnection pitches and diameters is modeled and the relationship of thermal resistance to interconnection pitch and diameter is obtained. The thermal resistance reduction by underfill with various interconnection pitches and diameters is also studied.

Assembly of mechanically compliant interfaces between optical fibers and nanophotonic chips

Silicon nanophotonics may bring disruptive advances to datacom, telecom, and high performance computing. However, the deployment of this technology is hampered by the difficulty of cost efficient optical inputs and outputs. To address this challenge, we have recently proposed a low-cost, mechanically compliant polymer interface between standard single mode fibers and nanophotonic waveguides. Our concept promises better mechanical reliability and better optical performance than existing technology. To manage the cost of assembly, we show here that self-alignment features can be effectively used to bridge the gap between the accuracy required by single-mode optics (1-2 um) and the capability of high-throughput microelectronic assembly equipment (~10 um). We describe the complaint interface, the assembly strategy, and the design of our re-alignment features. We demonstrate experimentally that misalignments at assembly as large as +/-10 um are re-aligned by our self-alignment structures to +/-1 to 2 um. Our approach enables existing microelectronics equipment to be used for singlemode optics assembly.

High-bandwidth, chip-based optical interconnects on waveguide-integrated SLC for optical off-chip I/O

As computing systems evolve for high performance with high power efficiency and exploit multi-core architecture, requirements for high-speed I/O are getting harder and could not be satisfied with optical interconnects. In addition to realize low power with optics by utilizing CMOS technology for high-sped driver circuits, chip-level packaging of optical integration are crucial to implement high-density optical channels, which are one of the requirements for the multi-core systems. Waveguide-integrated surface laminar circuit (SLC) have been developed for the chip-based, high-density optical interconnects. The power budget of optical link based on the chip-based optical interconnects are analyzed, since the budget affects the power dissipation of the link, and the fabrication process of the waveguides-integrated SLC is optimized to reduce the loss. This technology is then exploited into optical off-chip I/O for logic ICs, i.e. FPGA in this paper.

High-density optical interconnect exploiting build-up waveguide-on-SLC board

More optical channels have been implemented into computing systems as the system performance keeps increasing. Optical interconnects bring advantage of high data rate density, i.e. large bandwidth with small physical dimensions, as well as large bandwidth x distance product. High data rate density enables tight integration of many optical channels with electronic chips. One technique to implement such high density benefit is a printed circuit board (PCB) integrated with optical waveguides. In this paper, we will present an optical interconnect employing a waveguide- integrated surface laminar circuit (SLC) board. A build-up waveguide layer is formed on a SLC by laminating polymer films. Both optical and electronic chips are flip-chip mounted on the board. Optical signals are coupled with the waveguides by a 45-degree mirror formed on the waveguide. Electrical connections between the chips and the SLC circuits are provided by electrical vias through the waveguide layer. 10 Gbps operation has been demonstrated by a vertical-cavity surface-emitting laser (VCSEL) mounted on the waveguide-on-SLC board.

OE Device Integration for Optically Enabled MCM

We propose a new architecture of optical device integration on SLC carrier with capability of handling of the optical signals directly on MCM, or an optically enabled MCM, where VCSELs/PDs and the interface chips are placed closer to the main VLSI on a waveguide integrated SLC, while the optical connectors are at the periphery of the SLC carrier. This separated structure allows the highest number of optical channels per periphery length defined by the connector size, as well as the higher optical speed.

A novel dot‐pattern generation to improve luminance uniformity of LCD backlight

We report on a novel theoretical approach to generate irregular dot patterns, providing an integrated solution to difficulties peculiar to collimated -type backlight units. By applying this technology to a light guide and a diffuser film, the