Fumiaki Yamada

Sequential-color LCD based on OCB with an LED backlight

We have fabricated a 13.3-in. XGA (1024 × 768) TFT sequential-color liquid-crystal display using optically compensated birefringency (OCB), illuminated by an LED backlight. We fabricated the sequential-color display feasible process technology, and examined the performance and potential of a field-sequential-color scheme. The display was connected to a laptop computer and examined for flicker.

52.2: Invited Paper: Color Sequential LCD Based on OCB with an LED Backlight

We have fabricated a 13.3″ XGA (1024 by 768) TFT color sequential liquid crystal display using Optically Compensated Birefringency (OCB), illuminated by an LED backlight. We fabricated the color sequential display using mostly feasible process technology, and examined the performance and potential of a color field sequential scheme. The display was connected to a laptop computer and examined for flicker perception.

10 µm fine pitch Cu/Sn micro-bumps for 3-D super-chip stack

We develop novel micro-bumping technology to realize small size, fine pitch and uniform height Cu/Sn bumps. Electroplated-evaporation bumping (EEB) technology, which is a combination of Cu electroplating and Sn evaporation, is developed to achieve uniform height of Cu/Sn bumps. We develop CMOS compatible dry etching processes for removing sputtered Cu/Ta layers to achieve small size and fine pitch Cu/Sn bump. 5 µm square and 10 µm pitch Cu/Sn micro-bumps are successfully fabricated for the first time. Bump height variation is 5 µm ±3 % (95%, 2σ), which is uniform compared to electroplated Cu/Sn bumps. We evaluate micro-joining characteristics of Cu/Sn micro-bumps. Good I–V characteristics are measured from the daisy chain consisting of 1500 bumps with 10 µm square and 20 µm pitch. Resistance of Cu/Sn bump is 35 mΩ/bump, which is very low value compared to electroplated Cu/Sn bumps.

Investigations of cooling solutions for three-dimensional (3D) chip stacks

Three-dimensional (3D) chip stacks are receiving more attention for system performance enhancements. However, because of the higher circuit density, the cooling of 3D chip stacks gets more challenging. In conventional cooling methods, a heat sink or a micro-channel cooler is located at the top of the chip to dissipate the generated heat in a chip. In this paper, possible cooling methods from the bottom of a silicon interposer and cooling from the peripheral of a silicon interposer were proposed and evaluated. Based on the experimentally obtained thermal resistance of lead-free (SnAg) interconnections, the cooling performances of the above two cooling solutions were investigated by modeling and the requirements were clarified.

Experimental thermal resistance evaluation of a three-dimensional (3D) chip stack

To propose an appropriate cooling solution for a three-dimensional (3D) chip stack at the design phase, it is necessary to estimate the total thermal resistance of a 3D chip stack. The interconnection between stacked chips is considered as one of the thermal resistance bottleneck of a 3D chip stack, but it is not experimentally clear yet. We have previously measured the thermal conductivity of SnAg with Cu post to be 37–41W/mC by a steady state thermal resistance measurement method, using the sample which was simply composed of two Si chips and SnAg with Cu post between two Si chips. In this study, 3D stacked test chips are fabricated, which are implemented with PN junction diodes for temperature sensors and diffused resistors for heating, and the thermal conductivity of the interconnection in actual 3D stacked structure is experimentally obtained. The temperature distributions of two 3-layer-stacked-test-chips are measured and the equivalent thermal conductivity of the interconnection is experimentally obtained to be 1.6W/mC. This value is compared with the measured thermal conductivity of SnAg with Cu post (37–41W/mC) and its adequacy is examined.

Experimental thermal resistance evaluation of a three-dimensional (3D) chip stack, including the transient measurements

For the thermal management of three-dimensional (3D) chip stack, its thermal resistance needs to be clearly understood. In this study, 3D stacked test chips are fabricated, which are implemented with PN junction diodes for temperature sensors and diffused resistors for heating. At SemiTherm2011, the equivalent thermal conductivity of the interconnection, including BEOL (Back-End-Of-the-Line, wiring layer) is experimentally obtained to be 1.6W/mC and this time, we measure the thermal effect of Cu TSVs and it is experimentally supported that as the Cu TSV area ratio increases, the thermal conductivity of chip with TSVs in the vertical direction increases, on the contrary, that in the horizontal direction decreases. Also, the transient thermal measurement is performed and its result is compared with steady state measurement result. Further, the thermal capacitance measurement of 3D stacked test chip with hot spot heating is performed, which is essential to determine the transient thermal performance of 3D chip stack.

OE Device Integration for Optically Enabled MCM

We propose a new architecture of optical device integration on SLC carrier with capability of handling of the optical signals directly on MCM, or an optically enabled MCM, where VCSELs/PDs and the interface chips are placed closer to the main VLSI on a waveguide integrated SLC, while the optical connectors are at the periphery of the SLC carrier. This separated structure allows the highest number of optical channels per periphery length defined by the connector size, as well as the higher optical speed.

Thermal Stresses of Through Silicon Vias and Si Chips in Three Dimensional System in Package

Rbased on finite element method (FEM) was used to simulate the effects of voids formed inside Cu TSVs on the thermal conduction and mechanical stresses in the TSV structure. The thermal performance that was required in 3D SiP was estimated to ensure the reliability. Simulations for thermal stresses in the TSV structure in 3D SiP were carried out under thermal condition due to power ON/ OFF of device. In case that void was not present inside the TSV, the stresses in TSV were close to the hydrostatic pressure and the magnitude of the equivalent stress was lower than the yield stress of copper. Maximum principal stress of the Si chip in the TSV structure for the case without voids was lower than that of the bending strength of silicon. However, the level of the stresses in the Si chips should not be negligible for damages to Si chips. In case that void was present inside the TSV, stress concentration was occurred around the void in the TSV. The magnitude of the equivalent stress in the TSV was lower than the yield stress of copper. The magnitude of the maximum principal stress of the Si chip was lower than that of the bending strength of silicon. However, its level should not be negligible for damages to TSVs and Si chips. The stress on inner surfaces of Si chip was slightly reduced due to the presence of a void in the TSV. [DOI: 10.1115/1.4006515]

TSV diagnostics by X-ray microscopy

TSV (Through Silicon Via) is one of the key elements for building 3D integrated silicon devices with high bandwidth interconnections. In this paper, we propose a diagnostic method for TSV defects by using X-ray projection microscopy. By optimizing the image contrast of the X-ray projection micrographs in reference to its X-ray intensity histogram, we could obtain the small defect features in TSVs fast and non-destructively. Comparison between this X-ray observation and the destructive cross sectional observation agreed very well. We also extended the implementation of this X-ray microscope diagnostic method to 8-in. full wafer observation. We investigated the wafers with copper-filled TSVs with 80 µm and 20 µm diameters, and confirmed the feasibility of this method for an in-line process monitoring.

43.1: Color Filterless Liquid Crystal Display Illuminated with LEDs

We have prototyped a 13.3-inch diagonal color filterless LCD illuminated with LEDs. A new color directional backlight combined with a microlens attached liquid crystal cell plate shows the feasibility of a new power efficient LCD with better color and lead-free features.