Yong-Hun Kim

A 21-Gbit/s 1.63-pJ/bit Adaptive CTLE and One-Tap DFE With Single Loop Spectrum Balancing Method

This brief presents an adaptive continuous-time linear equalizer (CTLE) and one-tap decision feedback equalizer (DFE) using the spectrum balancing (SB) method. The SB method is extended for not only CTLE but also DFE with the aid of gain characteristics of one-tap DFE. Thus, adaptation loops for each equalizer type are merged to a single loop. As a result, the complexity and power consumption of the adaptation circuits are reduced significantly. The test chip consumes 34.2 mW from 1.2 V supply with 65-nm CMOS process.

An 11.5 Gb/s 1/4th Baud-Rate CTLE and Two-Tap DFE With Boosted High Frequency Gain in 110-nm CMOS

As the data rate has been increased over 10 Gb/s with copper interconnect, the intersymbol interference (ISI) caused from the channel loss should be compensated. While a decision feedback equalizer (DFE), which is widely used in the receiver can compensate the ISI, its ability to enhance the signal-to-noise ratio (SNR) is limited especially for high frequency data patterns (alternating data patterns). Even a DFE with a large number of taps, which has powerful compensation capacity for ISI, can improve only limited amount of SNR. To improve SNR, this brief presents a 1/4th baud-rate continuous-time linear equalizer (CTLE) and a two-tap DFE. The 1/4th baud-rate CTLE recovers data to be adequate for the DFE, and remaining ISI is removed by the DFE. To boost the high frequency gain of the DFE, exclusive OR merged adders are introduced, so the proposed equalizer is more tolerant against channel noise. It compensates 21.7-dB channel loss and operates with 11.5-Gb/s data rate as it consumes 25.35 mW from 1.3 V supply in a 110-nm CMOS technology.

A 10-Gb/s 0.71-pJ/bit Forwarded-Clock Receiver Tolerant to High-Frequency Jitter in 65-nm CMOS

This brief presents a power-efficient forwarded-clock receiver that is tolerant to high-frequency jitter by mixing filtered clock jitter to data. Due to mixing the filtered clock jitter, the proposed receiver does not include power-hungry delay lines but a phase interpolator, which enables saving significant power consumption. In a prototype receiver implemented in a 1-V 65-nm complementary metal-oxide-semiconductor process, it removes 2-GHz 0.7UI jitter modulated in data by an amount of 22%. It achieves 10 Gb/s with 0.71 pJ/bit in 10-cm FR4 channels and occupies 0.012 mm2.

An injection locked PLL for power supply variation robustness using negative phase shift phenomenon of injection locked frequency divider

This paper presents a 2 GHz injection-locked PLL (ILPLL) with an injection-locked frequency divider (ILFD). Using a negative phase shift phenomenon of the ILFD, injection timing can be calibrated without a delay line. As a result, the proposed ILPLL achieves a simple background injection timing calibration for robustness of power supply variation. The test core has been fabricated in 65nm CMOS process consuming 3.74mW at 0.9V supply voltage.

A 5-Gb/s Digital Clock and Data Recovery Circuit With Reduced DCO Supply Noise Sensitivity Utilizing Coupling Network

A digital clock and data recovery (CDR) is presented, which employs a low supply sensitivity scheme for a digitally controlled oscillator (DCO). A coupling network comprising capacitors, resistors, and coupling buffers enhances the supply variation immunity of the DCO and mitigates the jitter performance degradation. A supply variation-dependent bias generator produces the corresponding bias voltage to alleviate the supply variation with minimal area and power penalty. The proposed scheme improves 29.3 ps of peak-to-peak jitter and 11.5 dB of spur level, at 6 and 5 MHz 50 mVpp sinusoidal supply noise tone, respectively. Fabricated in a 65-nm CMOS process, the proposed CDR operates at 5-Gb/s data rate with BER . 10-12 for PRBS 31 and consumes 15.4 mW. The CDR occupies an active die area of 0.075 mm2.

An Input Data and Power Noise Inducing Clock Jitter Tolerant Reference-Less Digital CDR for LCD Intra-Panel Interface

This paper presents a reference-less digital clock and data recovery (CDR) for liquid crystal display (LCD) intra-panel interfaces. The increments of the display resolution, the color depth, and frame rate demand high speed transmission capacity between timing controller and source driver IC (SDIC). As the data rate increases, the performances of the CDR in the SDIC especially for the tolerance of input jitter and ground noise become important to recover the data without an error. This work exploits the half-bit previous input data with feed forward method and early/late signal from CDR to be tolerant to the input jitter and power noise. Two prototypes are tested with half-rate clocking at 5 Gb/s data rate, and quarter-late clocking at 10 Gb/s data rate. Both 5 Gb/s and 10 Gb/s prototypes improve the tolerance of the input jitter and power noise. Fabricated in 65 nm CMOS technology, the test chips consume 17.44 mW and 20.7 mW, respectively.

A 5-Gb/s 2.67-mW/Gb/s Digital Clock and Data Recovery With Hybrid Dithering Using a Time-Dithered Delta–Sigma Modulator

A digital clock and data recovery (CDR) employing a time-dithered delta-sigma modulator (TDDSM) is presented. By enabling hybrid dithering of a sampling period as well as an output bit of the TDDSM, the proposed CDR enhances the resolution of digitally controlled oscillator, removes a low-pass filter in the integral path, and reduces jitter generation. Fabricated in a 65-nm CMOS process, the proposed CDR operates at 5-Gb/s data rate with BER <; 10-12 for PRBS 31. The CDR consumes 13.32 mW at 5 Gb/s and achieves 2.14 and 29.7 ps of a long-term rms and peak-to-peak jitter, respectively.

A 20 Gbps 1-tap decision feedback equalizer with unfixed tap coefficient

This paper describes a 1-tap DFE with unfixed tap coefficient. According to the data patterns, the inter-symbol interference (ISI) is changed. The data patterns will be predicted using the DC level detector and the tap coefficient of the DFE will be adjusted to achieve high gain against high attenuation. The proposed 1-tap DFE with unfixed tap coefficient solves a high channel loss problem while it consumes low power. Designed in 65-nm CMOS technology, a 20 Gb/s receiver is composed of 1-tap half rate DFE with unfixed tap coefficient which compensates 20 dB attenuation, and it consumes 22.65 mW for 1-V supply.

A 10 Gb/s Reference-Less Baud-Rate CDR for Low Power Consumption with Direct Feedback Method

This brief presents a reference-less baud-rate digital clock and data recovery (CDR) with a data decision feedback (DDF) with a direct feedback method (DFM). The DDF with DFM has been used for the equalization of the channel loss for the serial link with a decision feedback equalizer. However, we apply DDF with DFM to the baud-rate CDR to reduce the number of data samplers, which is dropped to 2/3 compared to conventional baud-rate CDR. As a result, the power consumption and mismatch problem of the data samplers can be reduced. The test chip fabricated in 65-nm CMOS technology operates at a 10-Gb/s data rate with 13.84-mW power consumption.

A 0.65V, 11.2Gb/s Power Noise Tolerant Source-synchronous Injection-locked Receiver with Direct DTLB DFE

This brief presents a 0.65-V power noise tolerant source-synchronous injection-locked receiver with 13.4 dB channel loss compensation. To meet the 1UI timing constraint for the decision feedback equalizer in low supply, SR latches are removed in the feedback path and return to zero recovered data is used for equalization. Additionally, a power noise sensitivity of low supply is relieved by current and pMOS body bias control techniques of an oscillator. The test core fabricated in 65-nm CMOS process achieves 11.2 Gb/s with 0.303 pJ/bit FOM compensating 13.4 dB channel loss at 5.6 GHz.