Yong-Seo Koo

Analysis of the electrical characteristics of novel ESD protection device with high holding voltage under various temperatures

The paper introduces a silicon controlled rectifier (SCR)-based device with high holding voltage for ESD power clamp. The holding voltage can be increased by extending a p+ cathode to the first n-well and adding second n-well wrapping around n+ cathode. The increase of the holding voltage above the supply voltage enables latch-up immune normal operation. The device is fabricated by 0.35um BCD (Bipolar-CMOS-DMOS) technology and investigated not only the electrical characteristics, but also temperature dependence of holding voltage/current in a wide temperature range from 300K to 500K. In the measurement result, the proposed device has holding voltage of 8V and second breakdown current of 80mA/um. At high temperature condition of above 400K, the holding voltage, holding current and second breakdown current of the proposed device rapidly decrease.

The design of SCR-based dual direction ESD protection circuit with low trigger voltage

In this paper, a SCR(Silicon Controlled Rectifier)-based dual directional ESD protection circuit is proposed. The proposed protection circuit can provide effective protection for ICs against ESD (Electrostatic Discharge) in the both positive and negative directions. To analysis its electrical characteristics, it is verified through the TLP(Transmission Line Pulse) system. Also thermal reliability under high temperature conditions (300K-500K) is verified. In the measurement results, it has trigger voltage of 10.16V and holding voltage of 4.64V. It is shown that the proposed protection circuit has superior characteristics compared to the conventional SCR. In addition, these characteristics make the proposed protection circuit has area efficiency. As a result, the proposed dual directional ESD protection circuit can discharge ESD current in four stress mode (PD, ND, PS, NS) with superior characteristics and reliability.

Electrical characteristics of novel ESD protection devices for I/O and power clamp

This paper presents a novel silicon controlled rectifier (SCR)-based (Electrostatic Discharge) ESD protection devices for I/O clamp and power clamp. The proposed ESD protection devices has a high holding voltage and a low tigger voltage characteristic than conventional SCR. These characteristics enable to latch-up immune under normal operating conditions as well as superior full chip ESD protection. Also, the propsed devices can provide area efficiency in comparison to conventional (Gate Grounded NMOS) GGNMOS. The propsed devices are fabricated by using 0.35um BCD (Bipolar-CMOS-DMOS) technology. From the experimental results, the device for Input/Output (I/O) clamp has a trigger voltage of 6.5V, 7.7V and 8.1V with the LG1 of 0.5um, 0.8um and 1um, respectively. And the device for power clamp has a holding voltage of 8V, 10V and 11.3V with the D1 of 4.5um, 5.5um and 7um. Also, the device for I/O clamp has trigger voltage of 7.8V to 8.9V with the gate length (LG1) of 0.5um, 0.8um and 1.0um. Moreover, The proposed devices have high ESD robustness.

Electrical characteristics of the novel BiCMOS ESD protection circuit with low trigger voltage, low leakage and fast turn-on

In this paper, electrostatic discharge (ESD) protection circuit with an advanced substrate-triggered NMOS and a gate-substrate triggered NMOS using PNP bipolar transistor are proposed to provide low trigger voltage, low leakage, and fast turn-on speed. The experimental result show that the proposed substrate-trigged NMOS has a low trigger voltage of 5.98V and faster turn-on time(∼37ns). The proposed gate-substrate NMOS has a lower trigger voltage of 5.31V and low leakage current of 80pA.

The design of the novel BiCMOS ESD protection circuit with low trigger voltage and fast turn-on speed

In this paper, the design of the novel BiCMOS ESD protection circuit with low trigger voltage and fast turn-on speed is proposed. The proposed ESD protection circuit is verified by the transmission line pulse system. The results show that the novel BiCMOS ESD protection circuit has lower trigger voltage of 5.98V compared with that of conventional GGNMOS. And this ESD protection circuit has faster turn-on time of about 37ns than that of the conventional substrate-triggered ESD protection circuit. Also, the ESD protection circuit pass the ESD of HBM 3.2kV and MM 210V.

A Study on the Electrical Characteristic of SCR-based Dual-Directional ESD Protection Circuit According to Change of Design Parameters

In this paper, we proposed a dual-directional SCR (silicon-controlled rectifier) based ESD (electrostatic discharge) protection circuit. In comparison with conventional SCR, this ESD protection circuit can provide an effective protection against ESD pulses in the two opposite directions, so the ESD protection circuit can be discharged in two opposite direction. The proposed circuit has a higher holding voltage characteristic than conventional SCR. These characteristic enable to have latch-up immunity under normal operating conditions as well as superior full chip ESD protection. it was analyzed to figure out electrical characteristics in term of individual design parameters. They are investigated by using the Synopsys TCAD simulator. In the simulation results, it has trigger voltage of 6.5V and holding voltage increased with different design parameters. The holding voltage of the proposed circuit changes from 2.1V to 6.3V and the proposed circuit has symmetrical I-V characteristic for positive and negative ESD pulse.

The design of DC-DC Converter with DT-CMOS Switch

This paper is proposed DC-DC Converter with DT-CMOS (Dynamic Threshold voltage MOSFET) Switch. The proposed circuit is evaluated and compared with CMOS switch by both circuit simulation and device simulation. DT-CMOS switch reduces the output ripple and the conduction loss through a low on-resistance. Therefore, proposed converter has a excellent performance efficiency than converter with conventional CMOS switch. Proposed converter has switching frequency of 1.2MHz, 3.3V input voltage, 2.5V output voltage, and maximum current of 100mA. Also, this paper proposes two protection circuit in order to ensure the reliability. The first function is UVLO(under voltage lockout) and the second function is TSD(thermal shutdown). So, proposed converter can be protected from input under-voltage and over temperature.

Electrical characteristics of novel ESD protection devices for I/O clamp

This paper presents a novel silicon controlled rectifier (SCR)-based ESD protection devices for I/O clamp. The proposed ESD protection devices has a low trigger voltage and high holding voltage characteristics than conventional SCR. The proposed devices are fabricated by using 0.35um BCD (Bipolar-CMOS-DMOS) technology. From the experimental results, the device (PTSCR) for I/O clamp has a trigger voltage of 6.5V, 7.7V and 8.1V with the LG1 of 0.5um, 0.8um and 1um, respectively. The proposed ESD protection device (MPTSCR) has a lower trigger voltage of 5.6V. Also, the robustness has measured to human body model (HBM) 7kV and machine model (MM) 400V.

Low-dropout regulator using body-driven technique

Small size and high performance LDO regulator using body driven technique is presented in this paper. The body driven technique can decrease threshold voltage (Vth) and increase the current ID flowing from drain to source in current. The technique is applied to the error amplifier, voltage buffer and pass transistor to reduce chip size and maintain the same performance as conventional LDO regulator. The pass transistor using the technique can reduce the size 5.4% compared with conventional pass transistor at 150mA load condition. The proposed current mirror in error amplifier and voltage buffer can save the area about 61% compared with the conventional current mirror. The proposed LDO regulator works under the input voltage of 2.7V~4.5V and provides up to 150mA load current for an output voltage range of 1.2~3.3V.

SCR stacking structure with high holding voltage for high voltage power clamp

The latch-up immunity of high voltage power clamps used in high voltage ESD protection devices is rapidly becoming very important in high-voltage applications. The conventional high-voltage ESD devices are unsuitable for new high-voltage applications due to their low holding voltage, low ESD robustness, and their large size. In this study, a stacking structure with a high holding voltage and a high failure current is proposed and successfully verified using a 0.35um BCD (Bipolar-CMOS-DMOS) process in order to achieve the desired holding voltage and an acceptable failure current. The experiment results show that the holding voltage of the stacking structure can exceed the operational voltage found in high-voltage applications. In addition, the stacking structure can provide a high ESD robustness.