Jae-Chang Kwak

Design of a fully programmable shader processor for low power mobile devices

In this paper, we propose a novel architecture of a general graphics shader processor without a dedicated hardware. Recently, mobile devices require the high performance graphics processor as well as the small size and low power. The proposed shader processor is a GP-GPU (General-Purpose computing on Graphics Processing Units) to execute the whole OpenGL ES 2.0 graphics pipeline by using shader instructions. It does not require the separate dedicate H/W such as rasterization on this fully programmable capability. The fully programmable 3D graphics shader processor can reduce much of the graphics hardware. The chip size of the designed shader processor is reduced less than 60% in comparison with previous processors.

The design of the novel BiCMOS ESD protection circuit with low trigger voltage and fast turn-on speed

In this paper, the design of the novel BiCMOS ESD protection circuit with low trigger voltage and fast turn-on speed is proposed. The proposed ESD protection circuit is verified by the transmission line pulse system. The results show that the novel BiCMOS ESD protection circuit has lower trigger voltage of 5.98V compared with that of conventional GGNMOS. And this ESD protection circuit has faster turn-on time of about 37ns than that of the conventional substrate-triggered ESD protection circuit. Also, the ESD protection circuit pass the ESD of HBM 3.2kV and MM 210V.

A Design of Multi-threaded Shader Processor with Dual-Phase Pipeline Architecture

In this paper, Dual-Phase pipeline architecture and variable length instructions of a shader processor are proposed. The Dual-Phase pipeline architecture achieves a performance of dual core using a single core, and a parallelism of GP-GPU to accelerate graphic operations. For simplifying hardware, the register optimization is proposed. The variable length instructions are designed for efficient executions with less memory. Various pipeline hazards are resolved by a multi-threaded method. The proposed processor supports OpenGL ES 2.0. It has a size of 0.13Mlogic and shows the performance of 16.6MVertices/s, and 33.3MPixels/s

The Design of LVDS Transmitter with ESD Protection Circuit using BiCMOS Technologies

This paper presents the design of LVDS (low-voltage-differential-signaling) transmitter for Gb/s-per-pin operation using BiCMOS technology. To reduce chip area, LVDS transmitters switching devices are replaced with lateral bipolar devices. Also the proposed LVDS transmitter is operated at 1.8 V power supply. Its maximum data rate is 2.8 Gb/s approximately. In addition, an ESD protection circuit is designed for ESD protection. This structure has low latch-up phenomenon by using turn on/off character of N-channel MOSFET and low triggering voltage by turning P-channel MOSFET in the SCR structure. The triggering voltage is simulated to 4.5 V-8 V as the variation of gate length. Finally, the high speed I/O interface circuit with the low triggered ESD protection device is designed in a single-chip.

A study on the thermal reliability of high voltage MOSFET device

In this study, the electrical characteristics of high voltage MOSFET(HV-MOSFET) under high temperature were investigated. And, specific on-resistance, threshold voltage, trans-conductance, drain current of the HV-MOSFET were measured over a temperature range of 300 K les T les 450 K. The results of this study indicate that extended drift region length has a great effect on electrical characteristics, but that is does little effect on temperature dependence. The specific on-resistance increases slightly with temperature. Especially, at high temperature(at 450 K), the specific on-resistance increase about 30% than that in room temperature. And, in high temperature condition (at 400 K), drain current decrease about 30%, Also, transconductance(gm) decreases with temperature.

A design of a 3D graphics rasterizer with a culling and clipping

In this paper, we designed 3D graphics rasterizer with a culling and clipping for the efficient 3D graphics accelerator. The proposed rasterizer is implemented for the mobile system and process frustum culling, back face culling, Y-axis clipping and X-axis clipping. The rasterzier consists of triangle setup, edge walk and span process unit. Each unit of rasterzier is designed with a culling and clipping. It supports goraud shading with 16-bit depth values and 16-bit color values. The estimated performance of proposed rasterizer is 52M pixels per second.

A Study on the Electrical Characteristic of SCR-based Dual-Directional ESD Protection Circuit According to Change of Design Parameters

In this paper, we proposed a dual-directional SCR (silicon-controlled rectifier) based ESD (electrostatic discharge) protection circuit. In comparison with conventional SCR, this ESD protection circuit can provide an effective protection against ESD pulses in the two opposite directions, so the ESD protection circuit can be discharged in two opposite direction. The proposed circuit has a higher holding voltage characteristic than conventional SCR. These characteristic enable to have latch-up immunity under normal operating conditions as well as superior full chip ESD protection. it was analyzed to figure out electrical characteristics in term of individual design parameters. They are investigated by using the Synopsys TCAD simulator. In the simulation results, it has trigger voltage of 6.5V and holding voltage increased with different design parameters. The holding voltage of the proposed circuit changes from 2.1V to 6.3V and the proposed circuit has symmetrical I-V characteristic for positive and negative ESD pulse.

Implementation of multi thread management system on mobile GPGPU

This thesis is intended to design multi thread mobile GPGPU optimized in mobile environment, and to verify an effective thread management method of the multi thread mobile processor. For the verification of the multi thread management method, Lane detection algorithm was implemented to compare nVidias CUDA Architecture and the designed GPGPU in terms of thread management efficiency. The number of thread is normalized to 48 threads. An implemented Lane Detection Algorithm is composed of Gaussian filter algorithm and Sobel Edge Detection algorithm. As a result, the designed GPGPUs thread efficiency is up to 2 times higher than CUDAs thread efficiency.

Esd Protection circuits with low triggering vlotage, low leakage current and fast turn-on

ESD Protection circuits with low triggering voltage, low leakage current and fast turn-on using trigger techniques are presented in this paper. The proposed ESD protection devices are designed in 0.13um CMOS Technology. The results show that the proposed substrate Triggered NMOS using bipolar transistor has a lower trigger voltage of 5.98V and a faster turn-on time of 37ns. And the results show that the proposed gate-substrate triggered NMOS have lower trigger voltage of 5.35V and lower leakage current of 80pA.

Analysis of the electrical characteristics of LDMOSFET under various temperature

In this paper, we have investigated the electrical characteristics of power LDMOSFETs having different gate lengths(2.1 mum -3 mum) in the temperature range of 100 K-500 K. The specific on-resistance and the off-state breakdown voltage increase with temperature. The result shows that the specific on- resistance increases exponentially with the exponent of 2.2 and, by contrast, the off-state breakdown voltage increases linearly with a slope of 100 mV/K (Drift region concentration of measured device: 2 times 1015 cm-3). As a result, Ron/BV, known for a figure of merit of power device, increases with temperature.