Yuansheng Ma

Decomposition strategies for self-aligned double patterning

Spacer technology, a self-aligned double patterning (SADP) technique, has been drawing more and more attention due to its less stringent overlay requirements compared to other double-patterning methods. However, use of SADP techniques was previously limited by the lack of flexibility in terms of decomposition options , and significant developments were mainly implemented for 1D-type applications for memory. In this paper, we extend the SADP technique into the logic field. A matrix of design rule extraction structures was created by GLOBALFOUNDRIES, which was then decomposed into 2-mask SADP patterning solutions by Cadence Design Systems, and wafers were manufactured by Applied Materials. The wafers were processed in both positive and negative spacer tones, and then we evaluate the design capabilities of SADP for logic BEOL patterning on pitches from 56nm to 64nm. It shows that the SADP has big advantage over other pitch splitting techniques such as LELE in terms of design rules, overlay, and CD uniformity control. With SADP, the most challenging design rules for BEOL such as tip-to-tip and tip-to-line can be reduced 50% from 80 nm to 40 nm.

Challenges and opportunities in applying grapho-epitaxy DSA lithography to metal cut and contact/via applications

Directed self assembly has become a very attractive technology for Fin and contact/via applications. Some of the issues related to pattern placement error, defectivity rates and process integration are actively being addressed by the industry and have not faced significant roadblocks for contact-hole applications. While many DSA applications have been proposed, deploying DSA for Fin structures competes in cost and variability control with SADP techniques. Given the 1D nature of find structures, it is difficult to control fin placement with accuracy better than 4nm 3 sigma. In addition, a second patterning step is needed to remove the un-wanted sections of the grating and leaving behind only the required fin structures, therefore limiting its adoption. On the other hand, DSA applied to contact/via holes has demonstrated low defectivity rates due to improved polymerization and processing techniques, as well as an adequate control to reduce the placement error due to thermal fluctuations during the annealing and cylinder formation process. For that reason, the results from contact/via layers can extend to the metal cut layer printing with DSA grapho-epitaxy. In this paper, we show that DSA provides a promising cost-effective solution for the technology scaling by reducing mask number from N to N-1. It is shown that pxOPC may provide better guiding patterns than the conventional one. In addition, the practical grouping rules for DSA should avoid 2D grouping, avoid putting more than 3 features in a group with different pitches, and avoid grouping features with different sizes. Our recommendations to designers for DSA technology are the following: if the design is to be decomposed with 2 or more DSA masks, then the design rules should be set up in this way: first the minimum pitch is better to be on DSA material’s own natural pitch; second, for each DSA mask, singletons and bar-like grouping shapes with DSA’s natural pitch should be used as much as possible.

Considerations in Source-Mask Optimization for Logic Applications

In the low k1 regime, optical lithography can be extended further to its limits by advanced computational lithography technologies such as Source-Mask Optimization (SMO) without applying costly double patterning techniques. By cooptimizing the source and mask together and utilizing new capabilities of the advanced source and mask manufacturing, SMO promises to deliver the desired scaling with reasonable lithography performance. This paper analyzes the important considerations when applying the SMO approach to global source optimization in random logic applications. SMO needs to use realistic and practical cost functions and model the lithography process with accurate process data. Through the concept of source point impact factor (SPIF), this study shows how optimization outputs depend on SMO inputs, such as limiting patterns in the optimization. This paper also discusses the modeling requirements of lithography processes in SMO, and it shows how resist blur affect optimization solutions. Using a logic test case as example, the optimized pixelated source is compared with the non-optimized source and other optimized parametric sources in the verification. These results demonstrate the importance of these considerations during optimization in achieving the best possible SMO results which can be applied successfully to the targeted lithography process.

Incorporating DSA in multipatterning semiconductor manufacturing technologies

Multi-patterning (MP) is the process of record for many sub-10nm process technologies. The drive to higher densities has required the use of double and triple patterning for several layers; but this increases the cost of the new processes especially for low volume products in which the mask set is a large percentage of the total cost. For that reason there has been a strong incentive to develop technologies like Directed Self Assembly (DSA), EUV or E-beam direct write to reduce the total number of masks needed in a new technology node. Because of the nature of the technology, DSA cylinder graphoepitaxy only allows single-size holes in a single patterning approach. However, by integrating DSA and MP into a hybrid DSA-MP process, it is possible to come up with decomposition approaches that increase the design flexibility, allowing different size holes or bar structures by independently changing the process for every patterning step. A simple approach to integrate multi-patterning with DSA is to perform DSA grouping and MP decomposition in sequence whether it is: grouping-then-decomposition or decomposition-then-grouping; and each of the two sequences has its pros and cons. However, this paper describes why these intuitive approaches do not produce results of acceptable quality from the point of view of design compliance and we highlight the need for custom DSA-aware MP algorithms.

Calibration and application of a DSA Compact model for graphoepitaxy hole processes using contour-based metrology

Significant interest from the integrated circuit (IC) industry has been placed on directed selfassembly (DSA) for sub 10nm nodes. DSA is being considered as a cost reduction complementary process to multiple patterning (MP) and an enabler of new technology nodes. However, to realize the potential of this technology, it is essential to look holistically at the necessary infrastructure from the point of view of materials, hardware, software, process integration and design methodologies which enable its deployment in large volume manufacturing. One key aspect in enabling DSA processes is the ability to mirror functionality of full chip mask synthesis and verification methods of existing tools used in production. One of those critical components is the ability to accurately model the placement of the target phases in the DSA process with a given mask shape, as well as determining the conditions at which unwanted phase transitions start to occur. Self-consistent field theory and Monte Carlo1 simulators have the capability to probe and explore the mechanisms driving the different phases of a diblock copolymer system. While such methods are appropriate to study the nature of the self-assembly process, they are computationally expensive and they cannot be used to perform mask synthesis operations nor full chip verification. The nature of a compact model is to make a series of approximations allowing a simpler description of the problem in a way that the phenomena of interest can be sufficiently captured even if it is at the expense of its generality. In this case we focus our effort in establishing the minimum set of conditions that a compact model for the manufacture of contact holes using a grapho epitaxy process for a PS-PMMA diblock copolymer system needs. The processes uses etched short trenches as guiding patterns in which the vertical DSA cylinders are formed. By focusing in the phase of interest (i.e., cylinder forming conditions), it is possible to reformulate the problem in a phenomenological formulation which accounts for the interaction among cylinders, the volume fraction of the respective co-polymers and the interaction with the confinement walls. As such, a 2D approximation to the 3D environment can be applied too simplify thhe representation of the DSA process. This enables thee use of a 2D contour for compact model training and verification. Further simplification is not recommended due to the nature of the grapho-epitaxy guiding patterns, where a simple CD measurement is not sufficient to capture the 2D environment of post routed contact patterns for sub 10nm nodes. In this paper, we will study the application of the DSA compact model to a via layer of imec’s 7nm technology node standard cells. ArF immersion lithography will be used to pattern the guides, and the layout will be DSA compliant to determine the mask complexity as well as the sensitivity of the solution to mask biases for the contact layer.

Physical verification and manufacturing of contact/via layers using grapho-epitaxy DSA processes

This paper extends the state of the art by describing the practical material’s challenges, as well as approaches to minimize their impact in the manufacture of contact/via layers using a grapho-epitaxy directed self assembly (DSA) process. Three full designs have been analyzed from the point of view of layout constructs. A construct is an atomic and repetitive section of the layout which can be analyzed in isolation. Results indicate that DSA’s main benefit is its ability to be resilient to the shape of the guiding pattern across process window. The results suggest that directed self assembly can still be guaranteed even with high distortion of the guiding patterns when the guiding patterns have been designed properly for the target process. Focusing on a 14nm process based on 193i lithography, we present evidence of the need of DSA compliance methods and mask synthesis tools which consider pattern dependencies of adjacent structures a few microns away. Finally, an outlook as to the guidelines and challenges to DSA copolymer mixtures and process are discussed highlighting the benefits of mixtures of homo polymer and diblock copolymer to reduce the number of defects of arbitrarily placed hole configurations.

Directed self-assembly graphoepitaxy template generation with immersion lithography

Abstract. We present an optimization methodology for the template designs of subresolution contacts using directed self-assembly (DSA) with graphoepitaxy and immersion lithography. We demonstrate the flow using a 60-nm-pitch contact design in doublet with Monte Carlo simulations for DSA. We introduce the notion of template error enhancement factor (TEEF) to gauge the sensitivity of DSA printing infidelity to template printing infidelity and evaluate optimized template designs with TEEF metrics. Our data show that source mask optimization and inverse lithography technology are critical to achieve sub-80 nm non-L0 pitches for DSA patterns using 193i.

Modeling and Characterization of Contact-Edge Roughness for Minimizing Design and Manufacturing Variations in 32-nm Node Standard Cell

Despite intensive attention on line-edge roughness (LER), contact-edge roughness (CER) has been relatively less studied. Contact patterning is one of the critical steps in a state-of-the-art lithography process; meanwhile, the design rule shrinking leads to larger CER in contact holes. Since source/drain (S/D) contact resistance depend on contact area and shape, larger CER results in significant change in a device current. In this paper, we first propose a CER model based on power spectral density function which is a function of RMS edge roughness, correlation length, and fractal dimension. Then, we present a comprehensive contact extraction methodology for analyzing process-induced CER effects on circuit performance. In our new contact extraction model, we first dissect the contact with a same distance, and then calculate the effective resistance considering both the shape weighting factor and the distance weighting factor for stress induced CMOS cells. Using the results of CER, we analyze the impact of CER variation on the S/D contact resistance and the device saturation current. Results show that when the rms value of CER is 10nm, the S/D contact resistance and the device saturation current can vary by as much as 57.8% and 2.1%, respectively.

Modeling and characterization of contact-edge roughness for minimizing design and manufacturing variations

Despite intensive attention on line-edge roughness (LER), contact-edge roughness (CER) has been relatively less studied. Contact patterning is one of the critical steps in a state of the art lithography process; meanwhile, design rule shrinking leads to larger CER in contact holes. Since source/drain (S/D) contact resistance depends on contact area and shape, larger CER results in significant change in a device current. We first propose a CER model based on the power spectral density function, which is a function of rms edge roughness, correlation length, and fractal dimension. Then, we present a comprehensive contact extraction methodology for analyzing process-induced CER effects on circuit performance. In our new contact extraction model, we first dissect the contact with a same distance, and then calculate the effective resistance considering both the shape weighting factor and the distance weighting factor for stress-induced complementary metal-oxide semiconductor (CMOS) cells. Using the results of CER, we analyze the impact of both random CER and systematic variation on the S/D contact resistance, and the device saturation current. Results show that the S/D contact resistance and the device saturation current can vary by as much as 135.7 and 4.9%, respectively.

Compact model experimental validation for grapho-epitaxy hole processes and its impact in mask making tolerances

There has been significant research in the area of modeling self-assembling molecular systems. Directed self-assembly (DSA) has proven to be a promising candidate for cost reduction of processes which use double patterning and an enabler of new technology nodes. Self-consistent field theory and Monte Carlo simulators have the capability to probe and explore the mechanisms driving the different phases of a diblock copolymer system. While such methods are appropriate to study the nature of the self-assembly process, they are computationally expensive and they cannot be used to perform mask synthesis operations nor full chip verification. In this case we focus our effort in establishing the minimum set of conditions that a compact model for the manufacture of contact holes using a grapho epitaxy process for a PS-b-PMMA diblock copolymer system needs. The compact model’s main objectives are to find the guiding pattern that produces the lowest possible placement error, as well as verifying that the intended target structures are present after processing. Given that masks are not perfect, and lithographic process variations are not negligible, it is necessary to understand the mask requirements and the types of Optical Proximity Correction techniques that will be used to build guiding patterns. This paper explores the guiding pattern conditions under which proper assembly is achieved, and how the compact model formulation is able to determine placement of reliably assembling structures as well as identification of the guiding patterns which lead to improper assembly. The research leading to these results has been performed in the frame of the industrial collaborative consortium IDeAL focused on the development of Directed Self-assembly technique by block copolymers.