Yongsam Moon

An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance

This paper describes an all-analog multiphase delay-locked loop (DLL) architecture that achieves both wide-range operation and low-jitter performance. A replica delay line is attached to a conventional DLL to fully utilize the frequency range of the voltage-controlled delay line. The proposed DLL keeps the same benefits of conventional DLLs such as good jitter performance and multiphase clock generation. The DLL incorporates dynamic phase detectors and triply controlled delay cells with cell-level duty-cycle correction capability to generate equally spaced eight-phase clocks. The chip has been fabricated using a 0.35-/spl mu/m CMOS process. The peak-to peak jitter is less than 30 ps over the operating frequency range of 62.5-250 MHz, At 250 MHz, its jitter supply sensitivity is 0.11 ps/mV. It occupies smaller area (0.2 mm/sup 2/) and dissipates less power (42 mW) than other wide-range DLLs [2]-[7].

A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL

This paper describes an I/O scheme for use in a high-speed bus which eliminates setup and hold time requirements between clock and data by using an oversampling method. The I/O circuit uses a low jitter phase-locked loop (PLL) which suppresses the effect of supply noise. Measured results show peak-to-peak jitter of 150 ps and r.m.s. jitter of 15.7 ps on the clock line. Two experimental chips with 4-pin interface have been fabricated with a 0.6 /spl mu/m CMOS technology, which exhibits the bandwidth of 960 Mb/s per pin.

A 5-Gb/s 0.25-/spl mu/m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

A variable-interval oversampling clock/data recovery circuit (CDR) provides robust operation under varying jitter conditions. An eye-measuring loop in the CDR enables data recovery at maximum eye-opening, responding to the amount and shape of jitter. The CDR in 0.25 /spl mu/m CMOS shows <10/sup -13/ BER for 2/sup 7/-1 PRBS (pseudo-random-bit-sequence) at 5GBaud.

A 960 Mbps/pin interface for skew-tolerant bus using low jitter PLL

This paper describes an I/O scheme for use as a high-speed bus which eliminates setup and hold time requirements between clock and data by using oversampling method. The I/O circuit uses low jitter PLL which suppresses the effect of supply noise. Two experimental chips with 4 pin interface have been fabricated with 0.6 /spl mu/m CMOS technology, which exhibits the bandwidth of 960 Mbps per pin.

Clock dithering for electromagnetic compliance using spread spectrum phase modulation

As more electronic systems operate at higher frequencies and bandwidths, they tend to emit more electromagnetic interference (EMI). Due to lack of shielding, portable systems such as notebook computers have come under increasing pressure to comply with strict EMI emission regulations, such as FCC and CISPR. The data bus and the clock are major EMI sources because they conduct high currents and form large loops. This paper focuses on spreading the frequency-spectra of the clock and data signals to reduce their peak EMI emissions for EM compatibility. In a similar work, noise is intentionally injected onto a VCO control voltage in a clock PLL to achieve the effect of frequency modulation. In this case, the phase of the dithered clock varies unpredictably so mixing of both dithered and non-dithered clocks within the same system is avoided. In the proposed scheme, the phase difference between two arbitrary edges is limited within half a period. Hence, it is more practical in real system applications. Since it is implemented with a delay-locked loop (DLL), there are no PLL problems such as accumulated phase error, difficulties in designing stable loop filters, or area costs.

A quad 0.6-3.2 Gb/s/channel interference-free CMOS transceiver for backplane serial link

A quad-channel 0.6-3.2 Gb/s/channnel transceiver using eight independent phase-locked loops (PLLs) shows a 1-ps rms random jitter performance without interchannel interference. The PLL employs a folded starved inverter with high supply/substrate noise immunity and an analog coarse-tuning scheme for both seamless frequency acquisition and N-fold voltage-controlled-oscillator (VCO) gain reduction. A fixed-interval charge pumping is adopted for wide pumping-current range and large jitter tolerance. A wide-range delayed-locked loop (DLL) is utilized as a clock and reset generator for an elastic buffer. The transceiver, implemented in a 0.18-/spl mu/m CMOS technology, operates across a 30-in FR-4 backplane up to 3.2 Gb/s/ch with a bit-error rate of less than 10/sup -13/.

A Quad 6Gb/s Multi-rate CMOS Transceiver with TX Rise/Fall-Time Control

A multi-rate transceiver incorporating TX slew control with >2times range, PLL with <0.5times loop-filter area using capacitance multiplication, and DeltaSigmaZ-SSCG having 11.7dB peak reduction is designed in 0.13mum CMOS. Occupying 2.33mm2 with TX operable up to 8.5Gb/s, the quad transceiver consumes 386mW from 1.2V supply and has a BER<10-14 at 6Gb/s over an 8m cable with 22dB loss

A divide-by-16.5 circuit for 10-gb ethernet transceiver in 0.13-/spl mu/m CMOS

A divide-by-16.5 frequency divider, providing read- and write-clocks for an elastic buffer or a gearbox between 10.3125-Gb/s and quad 3.125-Gb/s transceivers in 10-G Ethernet application, is presented. The high-speed and noninteger division is designed by cascading high-speed divide-by-3 followed by divide-by-5.5 which uses double-edge-triggered flip-flops. The divide-by-3 circuit receives and generates 5.15625-GHz and 1.71875-GHz differential clocks with a 50% duty cycle, respectively. Based on current-mode logics (CMLs), the proposed divide-by-16.5 scheme is implemented in a 0.13-/spl mu/m CMOS technology to achieve over 5-GHz operation while consuming 18 mW from a 1.2-V supply.

A Low-Jitter Phase-Locked Loop Based on a Charge Pump Using a Current-Bypass Technique

A charge-pump circuit using a currentbypass technique, which suppresses charge sharing and reduces the sub-threshold currents, helps to decrease phase-locked loop (PLL) jitter without resorting to a feedback amplifier. The PLL shows no stability issues and no power-up problems, which may occur when a feedback amplifier is used. The PLL is implemented in 0.11-μm CMOS technology to achieve 0.856-ps RMS and 8.75-ps peak-to-peak jitter, which is almost independent of ambient temperature while consuming 4 mW from a 1.2-V supply.

A 500 MHz-to-1.2 GHz Reset Free Delay Locked Loop for Memory Controller with Hysteresis Coarse Lock Detector

This paper describes a reset-free delaylocked loop (DLL) for a memory controller application, with the aid of a hysteresis coarse lock detector. The coarse lock loop in the proposed DLL adjusts the delay between input and output clock within the pull-in range of the main loop phase detector. In addition, it monitors the main loop’s lock status by dividing the input clock and counting its multiphase edges. Moreover, by using hysteresis, it controls the coarse lock range, thus reduces jitter. The proposed DLL neither suffers from harmonic lock and stuck problems nor needs an external reset or start-up signal. In a 0.13-㎛ CMOS process, postlayout simulation demonstrates that, even with a switching supply noise, the peak-to-peak jitter is less than 30 ps over the operating range of 500-1200 ㎒. It occupies 0.04 ㎟ and dissipates 16.6 ㎽ at 1.2 ㎓.